NAND Memory Signal Boost Timing for Stack-Dependent Distortion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multistage stack configurations of NAND flash memory devices, signal quality deteriorates due to reflection effects, varying depending on the stacked position of NAND memory chips, making it challenging to uniformly improve signal quality across all chips.
Innovation Solution
A memory system with a controller that adjusts the addition period of a boost signal based on distortion characteristics specific to each memory chip, improving communication quality by emphasizing signal edges and expanding the eye aperture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multistage stack configuration is used to increase memory capacity, then memory capacity is improved, but signal quality deteriorates due to reflection effects
Solution Approach 1:
The patent applies local quality by adjusting the addition period of the boost signal individually for each memory chip based on its specific distortion characteristics. Each chip receives a customized signal adjustment parameter rather than a uniform setting, thereby optimizing signal quality locally for each chip position in the stack configuration.
Solution Approach 2:
The patent changes the parameter of the boost signal addition period to compensate for signal distortion. By varying the addition period parameter according to the distortion characteristics of each memory chip, the system optimizes signal quality while maintaining the multistage stack configuration for high capacity.
2Device complexity
If uniform signal adjustment is applied to all memory chips, then device complexity is reduced, but signal quality cannot be optimized for chips with different distortion characteristics
Solution Approach 1:
The control circuit determines different addition periods for the boost signal based on the specific distortion characteristics of each memory chip. This localized adjustment approach optimizes signal quality for each chip's position and electrical characteristics rather than applying a uniform setting to all chips.
Solution Approach 2:
The system dynamically adjusts the boost signal addition period according to the measured distortion characteristics of each memory chip. The control circuit modifies signal parameters in real-time based on chip-specific feedback, enabling adaptive optimization without requiring complex manual configuration.
3Reliability
If boost signal addition period is extended to improve signal quality, then eye aperture is expanded, but timing synchronization becomes more difficult to maintain
Solution Approach 1:
The patent optimizes the addition period parameter of the boost signal to achieve the minimum effective duration needed to expand the eye aperture. By precisely tuning this parameter for each chip rather than using excessively long durations, the system maintains timing synchronization while still improving signal quality.
Solution Approach 2:
The boost signal is applied periodically with a specific addition period that is optimized for each memory chip. This periodic application with controlled duration expands the eye aperture while maintaining consistent timing relationships, allowing synchronization to be preserved through regular, predictable signal patterns.
Data Source
AI summary
A memory system in an embodiment includes; one or more memory chips; and a controller connected to the one or more memory chips, the controller including a first driver configured to send a sending signal to the one or more memory chips, a second driver configured to generate a boost signal that is added to the sending signal, and a control circuit configured to set an addition period for the boost signal based on information relevant to a characteristic of distortion that occurs in the sending signal to the one or more memory chips.