Bit Line Discharge Current Control for Flash Memory
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Solution Overview
Problem
During read/program/erase operations in Flash memory, the high positive bias voltages applied to bit lines result in peak discharge currents that exceed safety limits, causing unexpected issues due to capacitance charging and subsequent discharge, which is not effectively managed by existing technologies.
Innovation Solution
A memory device with a current control circuit and discharge enable circuit that controls and limits the discharge current to a predefined value, eliminating peak currents and shortening discharge time by using a current mirror and staggered discharge enable signals to manage bit line discharge operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high positive bias voltages are applied to bit lines during read/program/erase operations, then the memory operations can be performed, but peak discharge currents are generated that exceed safety limits
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to a first voltage level before the actual read/program/erase operations. This preparatory charging step ensures that when high positive bias voltages are subsequently applied, the resulting discharge current peaks are controlled and remain within safety limits, thus enabling fast memory operations without harmful current spikes.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting voltage levels on bit lines through multiple charging stages. The bit lines are first charged to a first voltage level, then to a second voltage level during operations, and finally discharged to a third voltage level. This controlled parameter transformation enables efficient memory operations while preventing excessive discharge currents that would otherwise exceed safety thresholds.
2Loss of time
If bit lines are discharged quickly to reduce discharge time, then operational efficiency improves, but current control becomes more difficult and may exceed safety limits
Solution Approach 1:
The patent applies segmentation by dividing the bit line discharge process into multiple controlled stages rather than a single rapid discharge. The discharge occurs in steps with different current levels, allowing the system to reduce discharge time while maintaining current control within safety limits. This segmented approach prevents harmful current peaks while achieving fast discharge.
Solution Approach 2:
The patent implements periodic action through multi-stage charging and discharging cycles. Bit lines undergo periodic voltage transformations with distinct phases: initial charging to a first voltage level, charging to a second voltage level during operations, and controlled discharge to a third voltage level. This periodic control enables efficient time management while ensuring current safety throughout the process.
Data Source
AI summary
A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit coupled between the current control circuit and a ground. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. First terminals of the first transistors each is in connection with one of the bit lines. Second terminals of the first transistors each is in connection with the discharge enable circuit. Third terminals of the first transistors are in connection with a reference current generator of the current control circuit.