Gated Computing-in-Memory Cells for Fast Low-Power Data Processing

Solution Overview

Problem

The exponential growth of data generation outpaces data processing capabilities, leading to high time and power costs associated with accessing and processing data, as existing technologies are not optimized for simultaneous high-speed, power-efficient data access and processing across large memory arrays.

Innovation Solution

A computing-in-memory architecture that includes an array of gated computing cells, where each cell has a memory element and a logic element connected to a bit line, allowing for simultaneous access and computation by applying select signals to determine the data values stored in memory cells, thereby reducing the need for external processing and minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is accessed and processed using external processors, then data processing capability is improved, but time cost and power consumption increase

Engineering Contradiction:

Improvedata processing capabilityVSAvoidtime cost for data access

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent combines memory storage and logic processing functions into a single integrated memory device. Logic elements are embedded within the memory array, allowing data to be processed in-place without being transferred to external processors. This merging of storage and computation functions eliminates data movement overhead and reduces access time while maintaining processing capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces select signals as intermediaries that control which memory cells are accessed and processed. These select signals enable selective activation of specific memory cells containing logic elements, allowing efficient data access and processing without requiring external control logic. The select signals act as mediators between the control unit and the memory cells, reducing the time and power required for data access.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If data is accessed and processed using external processors, then data processing capability is improved, but power consumption increases

Engineering Contradiction:

Improvedata processing capabilityVSAvoidpower consumption for data access

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent combines memory storage and logic processing functions into a single integrated memory device. Logic elements are embedded within the memory array, allowing data to be processed in-place without being transferred to external processors. This merging of storage and computation functions eliminates data movement overhead and reduces access time while maintaining processing capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces select signals as intermediaries that control which memory cells are accessed and processed. These select signals enable selective activation of specific memory cells containing logic elements, allowing efficient data access and processing without requiring external control logic. The select signals act as mediators between the control unit and the memory cells, reducing the time and power required for data access.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If simultaneous access to multiple memory locations is enabled, then data access speed is improved, but device complexity increases

Engineering Contradiction:

Improvedata access speedVSAvoidmemory architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the memory device into multiple independently addressable memory cells, each containing a logic element. This segmentation allows simultaneous access to multiple memory locations through parallel selection of different cell addresses. Each memory cell can be independently controlled and accessed, enabling high-speed parallel data access without requiring complex interconnections between cells.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a universal select signal mechanism that can address and control any memory cell in the array through a standardized addressing scheme. This universal control interface simplifies the architecture by providing a single method for accessing multiple memory locations simultaneously, rather than requiring separate control logic for each cell. The logic elements within each cell are also multi-functional, capable of performing various logic operations based on the same structural framework.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12176063B2Computing-in-memory architecture

Publication Date: 2024.12.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.