Radiation-Resistant Memory Cell Using Cross-Coupled Latches

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Solution Overview

Problem

Memory cells, particularly in SRAM, are susceptible to errors due to strong radiation, which can change the stored voltage levels, leading to data corruption.

Innovation Solution

A circuit structure comprising cross-coupled latches and a read/write circuit that ensures both latches receive identical write signals, preventing radiation-induced changes by restoring the correct data state if one latch is affected.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional SRAM memory cell structure is used, then the device complexity is low, but the reliability under radiation exposure deteriorates

Engineering Contradiction:
Improveradiation resistanceVSAvoidmemory cell structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory cell is divided into two separate latches (first latch and second latch) that are cross-coupled. Each latch independently stores the same data bit, creating segmented redundancy that protects against radiation-induced errors. If one latch is affected by radiation, the other latch maintains the correct data state.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different functional qualities to different parts of the memory cell structure. The cross-coupled latches have identical structural quality for data storage, while the read/write circuit has specialized transistor configurations (first through fourth transistors) that provide differential write signal paths to ensure both latches receive the same data simultaneously.

Inventive Principle:
Principle #3Local quality

2Reliability

If cross-coupled latches with simultaneous write signals are implemented, then the radiation resistance is improved, but the device complexity increases

Engineering Contradiction:
Improvedata integrity under radiationVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cross-coupled latch structure serves multiple functions: it stores data in redundant form and simultaneously provides error correction capability. The read/write circuit with its differential transistor paths not only writes data but also ensures simultaneous updating of both latches, providing both data input and synchronization functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent creates a copy of the data storage function by implementing two identical latches that both store the same data bit. This copying approach ensures that if one latch is corrupted by radiation, the other latch contains an identical copy of the correct data that can restore the memory state.

Inventive Principle:
Principle #26Copying

3Object-affected harmful factors

If radiation shielding or filtering is applied, then the harmful radiation effects are reduced, but the device complexity and area increase

Engineering Contradiction:
Improveradiation exposureVSAvoidmemory cell area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The memory cell structure provides its own protection against radiation errors through the cross-coupled latch architecture. The system uses its internal redundancy and cross-coupling mechanism to automatically detect and correct radiation-induced errors without requiring external shielding or additional protection circuitry, thereby avoiding increased area overhead.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11862240B2Circuit structure and related method for radiation resistant memory cell
Publication Date: 2024.01.02 GLOBALFOUNDRIES US INC
  • US11862240B2 patent drawing
  • US11862240B2 patent drawing
  • US11862240B2 patent drawing

AI summary

Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.