Synapse String Array Using NAND Flash for Reliable Binary Neural Networks
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Solution Overview
Problem
Existing binary neural networks face challenges with low integration and reliability due to the use of unreliable MEMRISTOR-based synapses and logic gates, which result in high power consumption and heat issues, limiting their cognitive and learning capabilities.
Innovation Solution
A binary neural network is implemented using a synapse string array with high-reliability NAND flash memory cells and switching devices, configured to perform XNOR operations, enhancing integration and reducing power consumption through the use of MOSFETs or flash memory cell devices with charge storage layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MEMRISTOR-based synapses are used in binary neural networks, then cognitive function and learning capability are improved, but device reliability deteriorates and dispersion between devices increases
Solution Approach 1:
The patent changes the fundamental parameter of the synapse device from MEMRISTOR to NAND flash memory cell, utilizing different physical mechanisms (charge storage in floating gate vs. resistance change) to achieve both high reliability and cognitive functionality. This parameter change resolves the contradiction by selecting a device type with inherently better reliability characteristics while maintaining the required adaptability for neural network operations.
2Reliability
If logic gates are used to implement binary neural networks, then device reliability is improved, but degree of integration deteriorates
Solution Approach 1:
The patent merges the synapse function and neuron function into a single integrated structure using NAND flash memory cells. The synapse string array directly implements weighted summation, and the same structure supports neuron activation functions, eliminating the need for separate logic gate circuits and achieving high integration while maintaining reliability.
Solution Approach 2:
The NAND flash memory cell structure serves multiple functions simultaneously: it acts as the synapse device for weight storage, provides the neural network activation function through its charge storage characteristics, and enables both forward and backward propagation. This multi-functionality resolves the integration problem by making one structure perform what previously required multiple separate components.
3Productivity
If von Neumann architecture is used in integrated circuits, then computational functionality is maintained, but power consumption increases and heat release problems worsen
Solution Approach 1:
The patent replaces the von Neumann architecture's separate memory and processing units with an in-memory computing approach using NAND flash synapse strings. The computational operations (multiplication and accumulation) are performed directly within the memory structure through charge interactions, eliminating the need for data movement between separate memory and processing units, thereby reducing power consumption and heat generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high integration and reliability, enabling efficient cognitive functions while reducing power consumption and allowing for the implementation of more complex neural networks, including ternary neural networks, for advanced data recognition.
Implementation Method 1
the use of MOSFETs or flash memory cell devices with charge storage layers
Data Source
AI summary
Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.