Memory Power Gating With Level Shifting for Data Retention
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Solution Overview
Problem
Conventional non-volatile memory designs face challenges in data retention due to the dependency of signal inhibition on periphery voltage, leading to potential false writes and data corruption when core voltage is powered-up and clock is floating, necessitating an improvement in physical layout to prevent glitches and retain retention properties.
Innovation Solution
The implementation of power-gating architecture and self-deterministic level shifting circuitry that activates memory circuitry with a power-gated supply, shifting control signals between voltage domains to prevent glitches and ensure data retention, utilizing power-gating circuitry and level shifting mechanisms to manage voltage domains effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional NV memory designs are used with core voltage powered-up and periphery voltage powering-up later, then data retention cannot be saved, but implementing power-gating architecture increases device complexity
Solution Approach 1:
The memory system is segmented into distinct voltage domains: a first voltage domain for the memory core and a second voltage domain for control circuitry. This segmentation allows independent power management of each domain, enabling the memory core to retain data while control circuits are powered down, thus solving the data retention problem without requiring complete system shutdown.
Solution Approach 2:
Level shifting circuitry is introduced as an intermediary component between the first and second voltage domains. This intermediary enables controlled signal transfer across voltage domains while preventing glitches on the wordline, allowing safe power sequencing and activation without compromising data retention or requiring complex power management.
2Speed
If periphery voltage controls write inhibition signal, then signal rise time is delayed, but using power-gating circuitry increases manufacturing complexity
Solution Approach 1:
The write inhibition signal is generated in advance within the first voltage domain before the periphery voltage powers up. By preliminarily establishing the inhibition state in the memory core domain, the system avoids the delay caused by waiting for periphery voltage to rise, enabling immediate write protection upon core voltage activation.
Solution Approach 2:
Level shifting circuitry serves as an intermediary to transfer the write inhibition control from the second voltage domain to the first voltage domain. This intermediary mechanism enables direct control of write inhibition in the memory core domain independent of periphery voltage rise time, eliminating signal delay while maintaining manufacturable design through standardized voltage domain interfaces.
3Reliability
If clock is floating during power-up, then wordline may be triggered causing false write, but implementing protection circuitry increases device complexity
Solution Approach 1:
The write inhibition signal is activated in advance during the power-up sequence, before the clock signal becomes active. This preliminary anti-action ensures that even if the clock floats or transitions unexpectedly, the wordline cannot be triggered to cause a false write, protecting data integrity through preemptive inhibition rather than reactive protection circuitry.
Solution Approach 2:
Level shifting circuitry acts as an intermediary control mechanism that manages the write inhibition signal across voltage domains. This intermediary provides clean, controlled signal transitions that prevent glitches on the wordline during power sequencing, eliminating the need for additional protection circuitry while maintaining data integrity through standardized voltage domain interfacing.
4Adaptability or versatility
If DC power sequence is required for activation, then operational flexibility is reduced, but using power-gated supply increases control complexity
Solution Approach 1:
The power system is segmented into independent voltage domains with separate power gates. This segmentation allows each domain to be powered independently without requiring a fixed DC power sequence, enabling flexible power-up and power-down ordering while simplifying control through domain-independent power management.
Solution Approach 2:
The level shifting circuitry provides universal interfacing between voltage domains, enabling the same control mechanism to handle multiple power sequencing scenarios (core-first, periphery-first, simultaneous). This multi-functional intermediary eliminates the need for dedicated control logic for each power sequence variant, reducing overall control complexity while maintaining operational flexibility.
Data Source
AI summary
Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.