Data Strobe Reuse in Memory Duty Correction Training
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Solution Overview
Problem
Memory devices require significant time for performing read duty cycle correct training and write duty cycle correct training, as these operations are based on different signals.
Innovation Solution
A memory device configured to perform write duty cycle correct training by using a signal generated based on a signal used in read duty cycle correct training, incorporating a first duty correction circuit for read operations and a second duty correction circuit for write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read duty cycle correct training and write duty cycle correct training are performed based on different signals, then the training operations can be independently optimized for each signal type, but the total training time increases significantly
Solution Approach 1:
The patent merges the read duty cycle correct training and write duty cycle correct training operations by using the data strobe signal generated during read training as the basis for write training. The second duty correction circuit receives the data strobe signal from the first duty correction circuit and performs write duty cycle correction using this shared signal, thereby combining what were previously separate training processes into an integrated operation that reduces total training time while maintaining independent optimization capabilities
Solution Approach 2:
The data strobe signal generated during read duty cycle correct training is made multi-functional by using it as the basis for both read operations and write duty cycle correct training. The patent enables this signal to serve dual purposes: as the calibrated clock signal for read operations and as the reference signal for write training, thereby eliminating the need for separate write-specific training signals and reducing overall training time
2Reliability
If separate duty correction circuits are used for read and write operations, then each circuit can be optimized for its specific function, but the device complexity increases
Solution Approach 1:
The patent segments the duty correction functionality into two distinct circuits: a first duty correction circuit for read operations and a second duty correction circuit for write operations. Each circuit is specialized for its specific function, allowing independent optimization while maintaining clear functional separation. The first circuit processes read commands and generates the data strobe signal, while the second circuit uses this signal to perform write duty cycle correction, ensuring each segment can be optimized without compromising the other
Solution Approach 2:
The data strobe signal acts as an intermediary between the read and write duty correction circuits. The first duty correction circuit generates this signal through read training, and the second duty correction circuit receives and uses it as its input reference. This intermediary signal enables communication and coordination between the two specialized circuits without requiring direct integration or shared internal components, thereby maintaining functional independence while reducing overall system complexity
Data Source
AI summary
Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation.