Charge Trap Transistor Threshold Tuning for CMOS Variation Compensation
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Solution Overview
Problem
Process variation, mismatch, and temperature negatively impact the yield and performance of integrated CMOS circuits, particularly in smaller nodes like sub-32 nm nodes, leading to increased costs due to reduced chip yield and sensitivity to threshold voltage variability in SRAM and sense amplifiers.
Innovation Solution
The method involves changing the threshold voltage of charge trap transistors (CTTs) in a non-volatile multi-time programmable fashion using high-k dielectric materials, allowing for post-fabrication calibration and compensation of process variations by trapping or de-trapping charges, which remains effective even after disconnecting the chip from power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor size is reduced to achieve smaller CMOS nodes, then integration density increases, but process variation and threshold voltage variability worsen
Solution Approach 1:
The patent changes the electrical parameters of transistors by trapping or removing charges in the gate dielectric, which modifies threshold voltage and other electrical characteristics without changing the physical dimensions of the transistors. This allows compensation for process variation while maintaining small transistor sizes for high integration density.
Solution Approach 2:
The patent performs preliminary calibration by trapping charges during manufacturing to pre-compensate for process variations. This preliminary action adjusts transistor parameters before the chip is put into service, ensuring optimal performance despite manufacturing variations in smaller CMOS nodes.
2Reliability
If threshold voltage is adjusted to compensate for process variation, then circuit performance improves, but additional manufacturing complexity is introduced
Solution Approach 1:
The patent introduces charge traps as an intermediary mechanism between the gate dielectric and the channel. By controlling charge trapping, the system can adjust threshold voltage without requiring complex additional circuitry or manufacturing steps, thus improving reliability while minimizing manufacturing complexity.
Solution Approach 2:
The patent achieves threshold voltage adjustment by changing the electrical state (charge content) of the gate dielectric rather than modifying the physical structure. This parameter change approach simplifies manufacturing compared to structural modifications, as it uses standard high-k dielectric materials with controlled charge trapping properties.
3Adaptability or versatility
If high-k dielectric material is used to enable charge trapping, then non-volatile memory functionality is achieved, but device complexity increases
Solution Approach 1:
The patent makes the gate dielectric multi-functional by enabling it to serve both as an electrical insulator and as a charge storage medium. The high-k dielectric material provides both the necessary electrical isolation and the charge trapping capability, eliminating the need for separate memory structures and reducing overall device complexity.
Solution Approach 2:
The patent merges the functions of the gate dielectric and the memory storage element into a single component. By combining these functions, the system achieves non-volatile memory functionality without increasing device complexity, as the charge trapping occurs within the existing gate dielectric structure rather than requiring additional components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the yield and performance of integrated circuits by reducing the impact of process variations, enabling faster SRAM read operations, lower energy consumption, and non-volatile memory functionality without increasing transistor size, while also allowing for frequency tuning and obfuscation of chip functionality.
Implementation Method 1
changing a threshold voltage of at least one charge trap transistor (CTT) in a non-volatile multi-time programmable fashion. The at least one CTT may be fabricated using a high-k dielectric material as a gate dielectric
Data Source
AI summary
A method for changing functionality of an integrated circuit or improving performance of an integrated circuit, may include changing a threshold voltage of at least one charge trap transistor (CTT) in a nonvolatile multi-time programmable fashion. The at least one CTT may be fabricated using a high-k dielectric material as a gate dielectric. In some embodiments, the threshold voltage of the at least one CTT may be changed by increasing or decreasing the threshold voltage.