Multi-Plane Memory Control Using Shared Control Code Memory
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Solution Overview
Problem
Current memory devices require multiple control memories for each plane, leading to increased size and complexity, which hinders efficient control code management and operation across multiple planes.
Innovation Solution
A memory device architecture that utilizes a single control memory to store and manage control codes for multiple planes through a memory manager, micro-control circuits, and multiplexers, enabling sequential output of control codes to micro-control circuits for independent plane operations, thereby reducing the overall size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple control memories are used for each plane, then each plane can have dedicated control codes, but the overall size and complexity of the memory device increases
Solution Approach 1:
The patent merges multiple control memories into a single shared control memory that stores control codes for all planes. The control codes are organized with plane identification information, allowing the single control memory to serve multiple planes through selective output controlled by plane selection signals, thereby reducing overall device complexity while maintaining reliable control code management.
Solution Approach 2:
The single control memory is designed to be universal by storing control codes for multiple planes within the same memory structure. The control codes include plane identification fields that enable the same control memory to be used for controlling different planes, making the control memory multi-functional rather than requiring dedicated control memories for each plane.
2Reliability
If multiple control memories are used for each plane, then each plane can have dedicated control codes, but the size of the memory device increases
Solution Approach 1:
The patent merges multiple control memories into a single shared control memory that stores control codes for all planes. The control codes are organized with plane identification information, allowing the single control memory to serve multiple planes through selective output controlled by plane selection signals, thereby reducing overall device complexity while maintaining reliable control code management.
Solution Approach 2:
The single control memory is designed to be universal by storing control codes for multiple planes within the same memory structure. The control codes include plane identification fields that enable the same control memory to be used for controlling different planes, making the control memory multi-functional rather than requiring dedicated control memories for each plane.
3Device complexity
If a single control memory is used for multiple planes, then size and complexity are reduced, but control codes must be sequentially output to different micro-control circuits
Solution Approach 1:
The patent introduces plane selection signals as an intermediary mechanism that mediates between the single control memory and multiple micro-control circuits. These selection signals enable the control memory to selectively output control codes to the appropriate micro-control circuit based on the target plane, simplifying the overall structure while maintaining ease of operation through systematic code distribution.
Solution Approach 2:
The control codes stored in the single control memory are segmented by plane identification information. This segmentation allows the control memory to differentiate between control codes for different planes and output them to the corresponding micro-control circuits in sequence, making the sequential output operation systematic and manageable despite the shared memory structure.
Data Source
AI summary
The present technology includes a memory device which includes a plurality of planes in which data is stored, a peripheral circuit configured to perform operations on the plurality of planes, micro-control circuits configured to control the peripheral circuit so that the operations on the plurality of planes are independently performed, and a memory manager including a control memory in which different control codes for controlling the peripheral circuit are stored, and configured to output the control codes to the micro-control circuits, wherein the memory manager is configured to sequentially output a selected control code among the control codes to the micro-control circuits respectively corresponding to the planes.


