Programmable Logic in Flash Memory for Fast Error Correction
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Solution Overview
Problem
Semiconductor memory devices face challenges in implementing flexible and fast processing functions, such as word line bias settings, error correction, and build-in-self-test, which are difficult to achieve with regular hardware or firmware implementations.
Innovation Solution
Incorporating a programmable logic circuit with a lookup table and random access memory cells that can be configured using configuration information stored in non-volatile memory cells, allowing for dynamic configuration and operation after power-on, enabling flexible decision-making and fast processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If regular hardware or firmware implementations are used, then device complexity is reduced, but the ability to perform flexible and fast processing functions is limited
Solution Approach 1:
The patent implements a programmable logic circuit that can be dynamically configured after hardware validation through configuration information stored in non-volatile memory cells. This allows the logic circuit to adapt its functionality based on customer feedback and specific application requirements, transforming a static hardware implementation into a dynamic, reconfigurable system that achieves flexibility without requiring complete hardware redesign
Solution Approach 2:
The patent separates the configuration information from the logic circuit implementation by storing configuration data in non-volatile memory cells while using a programmable logic circuit (such as a lookup table-based circuit) to execute the functions. This segmentation allows independent optimization of memory storage and logic processing, enabling flexible function implementation without increasing overall device complexity
2Adaptability or versatility
If fixed hardware functions are implemented during fabrication, then manufacturing precision is maintained, but post-hardware validation functionality adjustment is impossible
Solution Approach 1:
The patent performs hardware validation and determines configuration information before final product deployment. Configuration information is prepared in advance based on validation results and customer feedback, then stored in non-volatile memory cells during or after fabrication. This preliminary action allows the hardware to be manufactured with standard precision while enabling post-fabrication functionality adjustment through pre-prepared configuration data
Solution Approach 2:
The patent changes the operational parameters of the logic circuit by loading different configuration information into non-volatile memory cells and subsequent volatile memory (such as SRAM). This parameter change approach allows the same hardware circuit to perform different functions by changing the configuration data, maintaining manufacturing precision while achieving post-hardware validation adaptability
3Reliability
If configuration information is stored in non-volatile memory cells, then data retention without power is achieved, but configuration loading time increases during power-on
Solution Approach 1:
The patent performs configuration loading as a preliminary action during the power-on initialization sequence. Configuration information is read from non-volatile memory cells and loaded into volatile memory (such as SRAM) before the device begins normal operation. This preliminary loading ensures that configuration data is readily available in fast access memory when needed, minimizing the impact on operational timing while maintaining reliable configuration retention
Solution Approach 2:
The patent implements continuous configuration availability by loading configuration information into volatile memory during power-on and maintaining it there throughout operation. This continuous presence of configuration data in fast access memory eliminates repeated reading from non-volatile memory during operation, reducing time loss while maintaining the reliability benefits of non-volatile storage for persistent configuration retention
Data Source
AI summary
Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions.