Memory Array Line Switching for Faster In-Memory MAC Sensing
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Solution Overview
Problem
Current AI structures face an IO bottleneck and inefficient multiply-accumulation (MAC) operations due to their process-centric architecture, which worsens with multi-bit inputs and weights, hindering high accuracy and efficiency.
Innovation Solution
The proposed operation method for a memory device involves strategic voltage switching of global signal lines, string select lines, and word lines to optimize the selection and sensing phases, reducing the background setup time for MAC operations and enhancing parallelism, thereby improving IMC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-bit inputs and weights are used for MAC operations to achieve high accuracy, then computational precision is improved, but the IO bottleneck worsens and processing efficiency decreases
Solution Approach 1:
The patent segments the bit lines into multiple groups, with each group associated with a dedicated global signal line. This segmentation allows parallel processing of multiple bit line groups simultaneously, increasing throughput while maintaining the precision benefits of multi-bit operations. Each segment can be independently controlled and sensed, resolving the bottleneck caused by centralized IO operations.
Solution Approach 2:
The patent introduces a new dimension of parallelism by adding global signal lines that operate independently from traditional word line control. This dimensional expansion allows MAC operations to proceed in parallel across multiple bit line groups, transforming the single-threaded IO bottleneck into a multi-threaded parallel processing architecture that maintains precision while improving efficiency.
2Speed
If the background setup time for multiplication operations is reduced to improve IMC performance, then processing speed is improved, but the reliability of voltage switching may deteriorate
Solution Approach 1:
The patent performs preliminary voltage setup on bit lines during previous operation phases, so that when MAC operations need to execute, the bit lines are already prepared with appropriate voltage levels. This preliminary action reduces the critical setup time required immediately before multiplication operations, increasing processing speed while maintaining reliable voltage transitions through advance preparation.
Solution Approach 2:
The patent maintains continuous voltage control on bit lines through overlapping operation phases, where voltage setup for one MAC operation begins before the previous operation completes. This continuous action eliminates idle setup time while ensuring voltage transitions remain controlled and reliable, as the voltage control circuitry remains actively engaged rather than switching abruptly.
Data Source
AI summary
A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.