3D Memory P-i-N Junction Hole Current Detection
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Solution Overview
Problem
Current three-dimensional semiconductor devices, such as vertical NAND strings, face challenges in achieving efficient memory storage and read operations due to limitations in their p-n junction structures and manufacturing processes.
Innovation Solution
A monolithic three-dimensional memory device is developed with a stack of alternating insulating and electrically conductive layers over a substrate, featuring a p-i-n junction structure that includes a doped semiconductor channel and upper drain region, allowing for efficient charge storage and read operations by measuring hole current passing through the semiconductor p-i-n junction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional p-n junction structure is used in three-dimensional vertical NAND strings, then the device can achieve basic memory storage functionality, but the read operation efficiency and memory storage capability are limited
Solution Approach 1:
The patent changes the electrical parameters of the junction structure by introducing a pinned layer with specific magnetic properties and controlling the thickness and composition of intermediate layers, thereby improving both storage capability and read efficiency through modified electrical characteristics
Solution Approach 2:
The patent employs composite material structures combining different semiconductor materials with distinct electrical properties in a vertical stack, creating a multi-layer p-n junction system that enhances memory performance through material property optimization
2Reliability
If the p-n junction structure is optimized for better performance, then memory storage and read operations improve, but the manufacturing process becomes more complex
Solution Approach 1:
The patent divides the semiconductor structure into distinct segmented layers with specific functions (tunneling layer, blocking layer, pinned layer, free layer), allowing each segment to be optimized independently while simplifying the overall manufacturing process through modular construction
Solution Approach 2:
The patent transitions from planar junction structures to vertical three-dimensional junction stacks, utilizing the vertical dimension to achieve improved performance while maintaining compatibility with existing manufacturing processes through vertical integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables enhanced memory storage capabilities and improved read operations by utilizing a p-i-n junction structure within the three-dimensional memory device, optimizing the p-n junction's performance and reducing manufacturing complexities.
Implementation Method 1
method reading thereof using hole current detection
Data Source
AI summary
Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.