3D Memory Pad Layout With Hybrid Bonding for Dense Routing
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Solution Overview
Problem
The scaling limitations of planar NAND memory cells and the challenges in fabricating 3D memory devices due to uneven topography and complex CMOS periphery circuits in 3D memory architectures.
Innovation Solution
A novel 3D memory device design with staggered conductive pads and conductive structures arranged in vertical planes, coupled with hybrid bonding of semiconductor structures to enhance memory density and reduce chip size, utilizing materials like W, Co, Cu, Al, and polysilicon for conductive pads and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar NAND memory cells are scaled to smaller sizes by improving process technology and fabrication process, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional 3D NAND memory architecture, stacking memory cells vertically to achieve higher density without proportionally increasing fabrication complexity. The 3D structure allows memory cells to be arranged in multiple layers along the vertical direction, effectively utilizing the third dimension for scaling.
2Quantity of substance
If 3D memory architecture is implemented to address density limitation, then memory density is improved, but topography uniformity and manufacturing precision deteriorate
Solution Approach 1:
The 3D memory structure is divided into multiple discrete layers including alternating dielectric layers and sacrificial layers. Each layer can be independently fabricated and controlled, allowing precise thickness control and uniformity maintenance across the entire stack. The segmented layer structure enables better management of topography variations compared to monolithic 3D structures.
3Ease of manufacture
If conductive pads are positioned above all conductive structures for simple routing, then ease of manufacture is improved, but chip area increases
Solution Approach 1:
Instead of uniformly positioning conductive pads above all conductive structures, the patent implements an asymmetric selective positioning where pads are placed only above specific conductive structures based on their electrical connection requirements. This asymmetric approach optimizes chip area utilization while maintaining manufacturing feasibility through reduced pad count and optimized routing paths.
4Area of stationary object
If hybrid bonding is used to couple semiconductor structures, then chip size is reduced and integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements preliminary alignment features and bonding preparation steps before the actual hybrid bonding process. Alignment marks, bonding pads, and surface preparation are performed in advance to ensure precise registration during bonding. This preliminary action reduces the actual bonding precision requirements by pre-establishing the geometric relationships between stacked structures.
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device can include: memory regions; a spacer region located between two adjacent memory regions, where the spacer region includes a dielectric stack and conductive structures extending through the dielectric stack along a vertical direction; and conductive pads above a subset of the conductive structures, where the conductive pads are arranged as two lines along a first direction and staggered with each other along a second direction, the first direction being perpendicular to the vertical direction and the second direction being perpendicular to both the first direction and the vertical direction.