3D Vertical Memory Array for Parallel Cell Access
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Solution Overview
Problem
Conventional memory devices face limitations in read/write throughput due to parallelism issues, as accessing multiple memory cells simultaneously leads to interference and voltage drops, inhibiting effective parallel access.
Innovation Solution
A 3D vertical memory array architecture with self-selecting memory cells, where word lines and bit lines are organized in planes separated by insulating material, allowing simultaneous access of multiple cells without interference through independent voltage control and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cells are accessed simultaneously in conventional memory arrays, then read/write throughput increases, but voltage drops and interference occur due to shared access lines
Solution Approach 1:
The memory array is divided into multiple independent sub-arrays, each with dedicated access lines. This segmentation allows simultaneous access to multiple sub-arrays without interference, as each sub-array operates independently with its own word lines and bit lines, eliminating the voltage drop and interference issues caused by sharing access lines.
Solution Approach 2:
The patent transitions from a two-dimensional memory array to a three-dimensional stacked architecture. Multiple memory sub-arrays are stacked vertically along the z-axis, allowing parallel access to cells across different layers. This dimensional expansion enables simultaneous read/write operations in multiple sub-arrays without the access line conflicts that limit two-dimensional arrays.
2Quantity of substance
If memory device size is reduced for scaling, then device density increases, but parallelism in access operations is limited
Solution Approach 1:
By stacking multiple memory sub-arrays vertically in the third dimension, the patent achieves high cell density without sacrificing parallelism. Each stacked sub-array maintains full access line independence, enabling simultaneous operations across layers. This 3D architecture decouples the trade-off between density and parallelism that plagues two-dimensional scaling.
Solution Approach 2:
Multiple memory sub-arrays are combined into a single stacked device, sharing common control and I/O interfaces while maintaining independent access lines. This merging approach achieves high density through vertical integration while preserving parallelism through independent sub-array operation, allowing the device to function as multiple parallel memory units.
3Device complexity
If access lines are shared among multiple memory cells, then device complexity is reduced, but current-driven voltage drops inhibit simultaneous cell access
Solution Approach 1:
The memory array is segmented into multiple sub-arrays, each with dedicated word lines and bit lines. This segmentation eliminates the need for complex voltage compensation schemes required in shared-access architectures. Each sub-array's access lines carry current independently, preventing voltage drops from affecting other simultaneously accessed cells, thus enabling straightforward simultaneous access.
Solution Approach 2:
The patent uses vertical stacking to multiply the number of independently accessible sub-arrays without proportionally increasing access line complexity. Each layer adds parallel capacity while using the same basic access line structure repeated across layers, achieving high simultaneous access capability with manageable complexity through modular 3D architecture.
Data Source
AI summary
The present disclosure provides a memory apparatus and a method for accessing a 3D vertical memory array. The 3D vertical memory array comprises word lines organized in planes separated from each other by insulating material, bit lines perpendicular to the word line planes, memory cells coupled between a respective word line and a respective bit line. The apparatus also comprises a controller configured to select multiple word lines, select multiple bit lines, and simultaneously access multiple memory cells, with each memory cell at a crossing of a selected word line and a selected bit line. The method comprises selecting a multiple word lines, selecting multiple bit lines and simultaneously accessing multiple memory cells, with each memory cell at a crossing of a selected word line of the selected multiple word lines and a selected bit line of the selected multiple bit lines. A method of manufacturing a 3D vertical memory array is also described.