3D Memory Chip Layout for On-Chip Passive Element Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in implementing on-chip passive elements due to space limitations, particularly in achieving sufficient inductance for inductors and integrating filters and delay logic without increasing chip size.
Innovation Solution
The semiconductor memory device employs a cell over peripheral (CoP) structure, where passive elements such as inductors, resistors, and capacitors are implemented in the remaining area of the first chip, connected to the peripheral circuits of the second chip, thereby enhancing the device's characteristics without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If passive elements are implemented on-chip to improve bandwidth and operating speed, then device performance is improved, but chip area increases
Solution Approach 1:
The patent implements passive elements in the remaining area of the first chip that overlaps with the peripheral area of the second chip in the vertical direction. This stacked three-dimensional arrangement allows passive elements to be integrated without increasing the planar chip footprint, effectively utilizing the vertical dimension to resolve the area constraint while enabling on-chip passive element functionality for improved operating speed and bandwidth.
2Reliability
If sufficient inductance is achieved for inductors, then filter performance is improved, but chip area increases
Solution Approach 1:
The patent achieves sufficient inductance by implementing the inductor using at least one metal layer among the plurality of metal layers of the first chip in the remaining area. This vertical stacking approach allows the inductor to achieve adequate inductance values for filter performance without requiring large planar area, as the multi-layer metal structure provides compact inductance generation in the vertical dimension.
3Area of stationary object
If passive elements are integrated without increasing chip size, then area efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor memory device into two separate chips: the first chip containing memory cells and passive elements in its remaining area, and the second chip containing core circuits and peripheral circuits. This segmentation allows passive elements to be integrated in the remaining area of the first chip without complicating the peripheral circuits on the second chip, managing device complexity through functional separation while maintaining area efficiency.
Solution Approach 2:
The patent uses the remaining area of the first chip as an intermediary region that hosts passive elements connecting to the peripheral circuits of the second chip. This intermediary arrangement allows passive elements to be integrated without directly increasing the peripheral circuit area on the second chip, managing integration complexity by providing a dedicated space for passive elements in the first chip's remaining area.
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor memory device includes: a first chip including a cell area and a remaining area, the cell area including a plurality of memory cells; and a second chip including a core area corresponding to the cell area and a peripheral area corresponding to the remaining area, the first chip and the second chip overlap along a vertical direction. Core circuits are provided in the core area of the second chip and peripheral circuits are provided in the peripheral area of the second chip. The core circuits and the peripheral circuits are configured to control operation of the plurality of memory cells, and passive elements connected to the peripheral circuits of the second chip are provided in the remaining area of the first chip.