3D Memory Structure for High-Speed Pattern Scanning
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Solution Overview
Problem
Current pattern scanning technologies are unable to achieve the high scan rates necessary for advanced applications, such as terabits/second, to support hundreds of thousands to millions of patterns and millions of active scan sessions, due to limitations in conventional memory architectures and processing capabilities.
Innovation Solution
A three-dimensional memory structure with multiple physical memory elements and distributed programmable finite state machines, along with a local result processor, is used to enhance bandwidth and processing efficiency, allowing for parallel operation and efficient handling of large data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory architecture is used, then device complexity is low, but scan rate cannot reach terabits/second
Solution Approach 1:
The patent transitions from conventional two-dimensional memory architecture to a three-dimensional memory structure with multiple stacked memory chips connected via vertical interconnects. This dimensional change enables significantly increased memory bandwidth and scan rate capability, achieving terabits/second processing speed while managing the added complexity through modular stacking.
Solution Approach 2:
The memory system is divided into multiple independent memory chips stacked vertically, each chip containing its own memory elements and control logic. This segmentation allows parallel data access across multiple memory layers, enabling the system to achieve high scan rates by processing data simultaneously across all memory stacks.
2Adaptability or versatility
If more patterns and scan sessions are supported, then adaptability improves, but processing capability becomes insufficient
Solution Approach 1:
The finite state machine (FSM) processing is divided into multiple parallel FSM instances distributed across different memory chips. Each FSM instance can independently process different patterns or scan sessions, allowing the system to support hundreds of thousands to millions of patterns and active scan sessions simultaneously while maintaining high processing capability through parallel execution.
Solution Approach 2:
By stacking multiple memory chips vertically and connecting them via interconnects, the system creates additional processing dimensions. This three-dimensional arrangement enables multiple FSM instances to operate in parallel across different vertical layers, significantly increasing the system's capacity to handle numerous patterns and scan sessions without sacrificing processing speed.
3Productivity
If data processing rate increases, then productivity improves, but memory bandwidth becomes insufficient
Solution Approach 1:
The patent implements a three-dimensional memory architecture where multiple memory chips are stacked vertically and connected through vertical interconnects. This dimensional change multiplies the effective memory bandwidth by enabling simultaneous data access across multiple memory layers, providing sufficient bandwidth to support terabits/second data processing rates.
Solution Approach 2:
Multiple memory chips are merged into a single integrated memory system through vertical interconnects, creating a unified memory space that can be accessed in parallel. This merging of multiple memory stacks provides aggregate bandwidth that satisfies the high data processing rate requirements while maintaining coherent memory access.
Data Source
AI summary
A method for performing enhanced pattern scanning includes the steps of: providing a three-dimensional memory structure including multiple physical memory elements; compiling multiple programmable finite state machines, each of the programmable finite state machines representing at least one deterministic finite automation data structure, the data structure being distributed over at least a subset of the physical memory elements; configuring a subset of the programmable finite state machines to operate in parallel on a same input data stream, while each of the subset of programmable finite state machines processes a different pattern subset; and providing a local result processor, the local result processor transferring at least a part of a match state from the deterministic finite automation data structures to corresponding registers within the local result processor, the part of the match state being manipulated being based on instructions embedded within the deterministic finite automation data structures.