CAD Circuit Design TRIZ Cases
- Feasibility Analysis for Electronic Assemblies
Computer method analyzes electronic assembly feasibility using functional architecture to resolve reliability versus time trade-offs.
- 3D Memory Structure for High-Speed Pattern Scanning
Stacked memory chips with distributed finite state machines process terabit streams, overcoming conventional bandwidth limits.
- Interactive Cloning for Semiconductor Layout Generation
Automated cloning applies source layouts to target elements within schematic diagrams.
- Mixed-Signal Low Power Verification via Analog Simulator Data
Analog simulator generates power connectivity data to verify mixed-signal designs without exhaustive transient simulation.
- Semiconductor Layout Decomposition for Odd-Even Feature Patterning
Segmenting substrates into odd and even feature zones allows double exposure patterning that resolves pitch doubling yield losses.
- Hierarchical Black Box for Graphical Modeling Execution Time
A hierarchical black box encapsulates subsystem blocks via callback functions to streamline graphical development workflows.
- Automated IBIS Model Generation from SPICE Netlists
A system generates IBIS models by rendering schematic symbols from SPICE netlists and translating operations into simulation commands.
- Connect Module Framework Dynamic Control
A connect module framework enables dynamic placement and interactive control of electronic design components.
- Combinational Loop Stability Verification via Fast Sequential Insertion
A verification system isolates combinational loops and inserts fast sequential elements to detect stability without altering design integrity.
- Multi-FPGA Prototyping Compiler for ASIC Circuit Partitioning
Compiler automates FPGA partitioning via circuit hierarchy analysis, reducing manual synthesis time while optimizing inter-module communication paths.
- Clock Alias Mechanism for IC Timing Analysis
A timing analysis mechanism defines clock aliases to correlate non-existent clocks with real ones in integrated circuit designs.
- Switch Server Traffic Processing with FPGA and Offloading
A switch server segments packet processing between CPUs and FPGAs to boost traffic capacity without adding servers.
- Core-Tile-Switch Mapping Architecture for On-Chip Bus Optimization
Many-to-many core-tile-switch mapping minimizes hop distance to reduce communication delay time and energy consumption in network-on-chip architectures.
- DPE Array Global Mapping via ILP for Runtime Reduction
Integer linear programming maps program nodes to data processing engine arrays, optimizing placement and buffer assignment.
- FPGA Security via Extended Signal Path Runtime
Synthesis conditions extend FPGA signal path runtime beyond one clock cycle to block unauthorized configuration file generation.
- EDA Synchronizer Chain Optimization for Metastability
Automated EDA tool identifies and protects synchronizer chains using timing relationships to ensure robust data transfer between clock domains.
- Hierarchical CDC and RDC Verification for SoC IP Cores
Hierarchical verification cross-checks functional assumptions against structural analysis of IP cores to resolve incomplete SoC design checks.