DPE Array Global Mapping via ILP for Runtime Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

There is a lack of efficient processor-based systems capable of compiling applications for heterogeneous data processing architectures, particularly for mapping kernels and input/output nodes within a data processing engine (DPE) array, which results in high runtime and complexity due to the mismatch between global and detailed placement requirements.

Innovation Solution

The implementation of global and detailed mapping techniques using Integer Linear Programming (ILP) algorithms to map program nodes in a netlist to components within a DPE array, minimizing communications and wirelength, and assigning buffers to memory banks, thereby reducing runtime and improving solution convergence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If global mapping is performed without considering detailed placement requirements, then the mapping process is simpler, but the runtime and solution quality deteriorate

Engineering Contradiction:
Improvemapping process complexityVSAvoidruntime
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The mapping process is divided into two distinct phases: global mapping that considers detailed placement requirements from the outset, and a subsequent detailed placement phase. This segmentation allows each phase to focus on specific optimization goals while incorporating constraints from the other phase, resolving the contradiction between process simplicity and runtime efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Detailed placement requirements are identified and incorporated during the global mapping phase itself, rather than being added as a separate subsequent step. This preliminary action ensures that the global mapping is performed with awareness of detailed placement constraints, improving solution quality without significantly increasing overall complexity.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If traditional mapping methods are used, then the implementation is straightforward, but the solution convergence and runtime performance worsen

Engineering Contradiction:
Improveimplementation easeVSAvoidsolution convergence
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The mapping approach changes the parameter of consideration by incorporating detailed placement requirements as explicit constraints during global mapping. This parameter change transforms the optimization problem to converge faster by avoiding suboptimal global mappings that would require extensive detailed placement adjustments later.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Detailed placement requirements serve as an intermediary constraint that mediates between global mapping objectives and final placement quality. By introducing this intermediary consideration during global mapping, the system achieves better solution convergence while maintaining implementation feasibility through a systematic two-phase approach.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If clusters of kernels are not mapped to DPE cores optimally, then the mapping process is simpler, but communication overhead and wirelength increase

Engineering Contradiction:
Improvemapping algorithm complexityVSAvoidcommunication overhead
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The global mapping process incorporates local quality considerations by taking detailed placement requirements into account during the global phase. This ensures that clusters of kernels are mapped to DPE cores with awareness of local communication needs, reducing communication overhead and wirelength without requiring excessively complex post-processing adjustments.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10853541B1Data processing engine (DPE) array global mapping
Publication Date: 2020.12.01 XILINX INC
  • US10853541B1 patent drawing
  • US10853541B1 patent drawing
  • US10853541B1 patent drawing

AI summary

Some examples described herein relate to global mapping of program nodes of a netlist of an application. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to obtain a netlist of an application. The netlist contains program nodes and respective edges between the program nodes. The application is to be implemented on a device comprising an array of data processing engines. The processor is also configured to execute the instruction code to generate a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generate a detailed mapping of the program nodes based on the global mapping; and translate the detailed mapping to a file.