Core-Tile-Switch Mapping Architecture for On-Chip Bus Optimization
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Solution Overview
Problem
Conventional on-chip bus architectures face challenges in minimizing energy consumption and communication delay time due to inefficient core-tile-switch mapping methods, which often consider only one-to-one mapping and do not optimize for hop distance, leading to suboptimal performance as integration increases.
Innovation Solution
An optimized core-tile-switch mapping method is developed, which creates a core communication graph and Network-on-chip architecture, using a mathematical approach to map cores to tiles and switches, minimizing hop distance by calculating and optimizing data communication flow and volume across the network, ensuring efficient data transmission and reduced energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional one-to-one core-tile-switch mapping is used, then the mapping is simple to implement, but the hop distance between cores is not minimized leading to higher energy consumption and communication delay
Solution Approach 1:
The patent changes the mapping parameters from simple one-to-one correspondence to many-to-many mapping relationships. By allowing multiple switches to be mapped to multiple tiles and cores, the system can optimize hop distance and reduce energy consumption while maintaining implementation feasibility through automated mapping algorithms.
Solution Approach 2:
The mapping architecture is made dynamic by allowing flexible many-to-many relationships between cores, tiles, and switches. This dynamic mapping enables the system to adapt to different communication patterns and minimize hop distance based on actual data transmission requirements, thereby reducing energy consumption.
2Device complexity
If conventional one-to-one core-tile-switch mapping is used, then the mapping structure is simple, but communication delay time increases due to suboptimal hop distance
Solution Approach 1:
The patent transforms the mapping structure from rigid one-to-one to flexible many-to-many relationships. This parameter change enables optimization of communication paths by considering multiple switching routes, thereby reducing hop distance and communication delay time while managing structural complexity through systematic mapping algorithms.
Solution Approach 2:
The mapping approach adds dimensional flexibility by establishing many-to-many relationships across multiple cores, tiles, and switches simultaneously. This multi-dimensional mapping enables the system to find optimal communication paths that minimize hop distance and reduce communication delay time.
3Productivity
If high integration system-on-chip is implemented, then product size decreases and development time reduces, but wire characteristics become significant making desired system performance difficult to obtain
Solution Approach 1:
The patent segments the on-chip communication architecture into distinct functional elements: cores, tiles, and switches with many-to-many mapping relationships. This segmentation allows independent optimization of each component and enables better control over signal characteristics, maintaining system performance despite high integration.
Solution Approach 2:
The patent introduces intermediate mapping layers between cores and switches through tiles. This intermediary mapping structure acts as a buffer that manages the complexity of direct high-density connections, allowing systematic control over wire characteristics while achieving high integration and maintaining desired system performance.
Data Source
AI summary
There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches; and mapping the cores to the tiles using a predetermined optimized mapping method to thereby create the optimized core-tile-switch mapping architecture. The optimized mapping method includes first, second, and third calculating steps. According to the optimized core-tile-switch mapping architecture creating method and the computer-readable recording medium for recording the method, since the hop distance between cores is minimized, it is possible to minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the optimized mapping architecture presents a standard for comparing the optimization of other mapping architectures.