Multi-FPGA Prototyping Compiler for ASIC Circuit Partitioning
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Solution Overview
Problem
The existing methods for prototyping ASIC circuits using a multi-FPGA system are inefficient, requiring manual estimation and synthesis tools, leading to suboptimal solutions and lengthy processes that can take up to six months without guaranteeing an optimal result.
Innovation Solution
An automated compiler-based approach that utilizes circuit hierarchy to partition design instances between FPGAs, optimizing resource usage and inter-module communication, and employs signal multiplexing and negotiation-based routing to maximize system frequency and reduce inter-FPGA signal congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual estimation and synthesis tools are used to determine FPGA configuration, then the process can be completed with existing tools, but the development time becomes excessively long (up to six months) and optimal solutions are not guaranteed
Solution Approach 1:
The system performs automatic partitioning and configuration of FPGAs through an integrated compiler that autonomously analyzes the ASIC circuit design, determines optimal FPGA allocation, and generates configuration files without requiring manual intervention or external synthesis tools, enabling the system to serve itself in the prototyping process
Solution Approach 2:
The compiler performs preliminary analysis of the ASIC circuit hierarchy and pre-determines the optimal FPGA configuration and signal routing before actual prototyping begins, eliminating the need for iterative manual adjustment and synthesis that characterizes traditional approaches
2Adaptability or versatility
If manual partitioning of ASIC into FPGAs is performed, then flexibility in adjusting the configuration is maintained, but the complexity of the process increases and optimal resource utilization is difficult to achieve
Solution Approach 1:
The manual mechanical process of partitioning and configuring FPGAs is replaced by an automated electronic compiler system that algorithmically analyzes circuit hierarchy, performs optimization, and generates configurations, substituting human-operated mechanical processes with automated electronic computation
Solution Approach 2:
The system automatically adjusts critical parameters including the number of FPGAs, signal routing configurations, and resource allocation based on circuit complexity requirements, transforming the static manual configuration process into a dynamic automated optimization process that adapts parameters according to the specific design needs
3Ease of manufacture
If the number of FPGAs and connections is manually estimated, then the initial configuration can be established, but the solution is suboptimal and may require iterative removal or addition of FPGAs
Solution Approach 1:
The compiler incorporates feedback mechanisms that automatically evaluate the optimality of the generated FPGA configuration and routing, and iteratively refine the solution by adjusting FPGA allocation and signal paths until optimal resource utilization is achieved, eliminating the need for manual iterative adjustments
Data Source
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AI summary
The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of: - partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising: - inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; - and the number of crossings of programmable chips of a critical combinatorial path; - establishing a routing of the signals between programmable chips using the physical resources available.