Combinational Loop Stability Verification via Fast Sequential Insertion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for handling combinational loops in electronic design verification are inefficient, as they often require manual inspection, lead to false positives and negatives, and involve complex serial analysis, which can be impractical and time-consuming, especially when dealing with large designs and shared loop paths.
Innovation Solution
A computer-implemented method that isolates combinational loops and inserts sequential elements with clocks faster than the system clock to determine stability using formal verification, allowing for parallel analysis without altering the design's functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual inspection is used to analyze combinational loops, then verification accuracy may be improved, but productivity deteriorates due to time-consuming analysis
Solution Approach 1:
The patent introduces an intermediary tool that automatically identifies and analyzes combinational loops by injecting test patterns and capturing waveforms. This intermediary system bridges the gap between manual verification accuracy and automated analysis speed, allowing engineers to verify loop stability without manual inspection of each loop.
Solution Approach 2:
The patent replaces the mechanical process of manual loop inspection with an automated electronic verification system. The system uses automatic test pattern injection, waveform capture, and stability analysis to substitute human manual analysis, thereby maintaining verification accuracy while dramatically improving productivity.
2Reliability
If dual-rail model is used to analyze loops, then reliability of loop classification is improved, but device complexity worsens due to duplication of logic
Solution Approach 1:
The patent extracts only the necessary portions of the design for loop verification by automatically identifying combinational loops and isolating them for analysis. Instead of duplicating entire logic blocks as in dual-rail modeling, the system extracts minimal test patterns and captures only the relevant loop waveforms, thereby maintaining reliability while reducing complexity.
Solution Approach 2:
The patent segments the verification process into distinct phases: loop identification, test pattern injection, waveform capture, and stability analysis. This segmentation allows the system to handle complex designs by breaking them into manageable loop instances, verifying each independently without requiring full dual-rail duplication of the entire design.
3Reliability
If serial analysis of loops is performed, then reliability of each loop verification is improved, but productivity deteriorates due to sequential processing
Solution Approach 1:
The patent implements periodic action by systematically iterating through identified loop instances in an automated sequence. The system cycles through each loop, injecting test patterns and capturing waveforms in a structured periodic manner, which maintains verification reliability while improving throughput through automation compared to manual serial analysis.
4Ease of operation
If loop paths are broken for verification, then ease of operation is improved, but reliability worsens due to potential false positives and negatives
Solution Approach 1:
The patent uses waveform capture and stability analysis as an intermediary method that verifies loop behavior without physically breaking the loop paths. The system injects test patterns, captures the actual waveforms circulating in the loops, and analyzes stability mathematically, thereby maintaining the integrity of the original design while achieving verification ease and reliability.
Data Source
AI summary
The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using at least one processor, an electronic design and isolating a combinational loop associated with the electronic design. Embodiments may further include inserting a sequential element in a loop path of the combinational loop, wherein the sequential element has a clock that is at least twice as fast as a fastest system clock associated with the electronic design. Embodiments may also include generating a property that determines whether an input and an output of the sequential element is never different and determining whether the property is true using formal verification.