Clock Alias Mechanism for IC Timing Analysis
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Solution Overview
Problem
Integrated circuit design faces challenges in timing analysis due to differing clock names between third-party logic blocks and the rest of the design, requiring manual duplication of clocks, which is time-consuming and prone to errors.
Innovation Solution
A timing analysis mechanism that allows defining clock aliases to correlate non-existent clocks with real clocks, either by modifying user assertions to reference real clocks or generating duplicate clocks in the timing database, enabling efficient processing without manual duplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual duplication of clocks is performed to handle different clock names in third-party logic blocks, then timing analysis can be performed, but the process becomes time-consuming and error-prone
Solution Approach 1:
The patent introduces a clock aliasing mechanism that acts as an intermediary between different clock name conventions. The system automatically creates aliases that map third-party clock names to the design's internal clock names, eliminating the need for manual duplication while ensuring accurate timing analysis. This intermediary layer resolves the naming conflict without requiring designer intervention.
Solution Approach 2:
The timing analysis tool performs self-service by automatically detecting and resolving clock name conflicts between third-party logic blocks and the main design. The system autonomously creates clock aliases, maps them to corresponding real clocks, and updates user assertions without requiring manual intervention from the designer, thus saving time while maintaining accuracy.
2Adaptability or versatility
If manual creation of duplicate clocks is required, then clock name conflicts can be resolved, but the complexity and error rate increase significantly
Solution Approach 1:
The clock aliasing mechanism serves as an intermediary that automatically handles the mapping between different clock name conventions. Instead of requiring manual creation of duplicate clocks, the system creates automated aliases that preserve the original clock names from third-party blocks while integrating them with the design's internal clock infrastructure, reducing complexity while maintaining compatibility.
Solution Approach 2:
The patent implements automated copying of clock characteristics through aliasing. Rather than manually creating duplicate clocks with copied attributes, the system creates aliases that automatically inherit all clock attributes (period, duty cycle, skew, etc.) from the source clock, ensuring accurate replication without manual intervention and reducing the risk of errors.
3Productivity
If user assertions are rewritten to use consistent clock names, then timing analysis can proceed, but the rewriting effort is time-consuming and must be repeated for updates
Solution Approach 1:
The clock aliasing mechanism acts as an intermediary layer that automatically translates clock names in user assertions. When a third-party logic block with different clock names is integrated, the system automatically creates aliases and updates all user assertions to reference the correct clock names, eliminating the need for manual rewriting and ensuring consistency across the design.
Solution Approach 2:
The system performs preliminary action by automatically creating clock aliases and updating user assertions before timing analysis begins. This preliminary processing ensures that all clock name conflicts are resolved in advance, allowing the timing analysis to proceed without interruptions for manual rewriting or verification of assertion consistency.
4Reliability
If duplicate clocks are manually created to mimic base clock behavior, then timing analysis can be performed, but updates to base clock attributes must be manually propagated
Solution Approach 1:
The clock aliasing mechanism serves as an intermediary that automatically propagates attribute updates from base clocks to aliased clocks. When base clock attributes such as period, duty cycle, or skew are updated, the system automatically updates all aliases referencing those base clocks, eliminating the need for manual propagation while ensuring timing analysis accuracy is maintained.
Solution Approach 2:
The system implements feedback mechanisms that automatically detect and propagate changes in base clock attributes to all dependent aliases. When a base clock attribute is modified, the system feedbacks this change to all aliases, ensuring they reflect the updated characteristics, thus maintaining timing analysis accuracy without manual intervention.
Data Source
AI summary
A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.