Hierarchical CDC and RDC Verification for SoC IP Cores
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Solution Overview
Problem
Current CDC and RDC verification tools for SoC design do not adequately verify assumptions at the individual IP core level, leading to incomplete analysis and reduced design efficiency in addressing clock domain crossing and reset domain crossing issues.
Innovation Solution
A method and apparatus for hierarchical CDC and RDC verification that involve obtaining data models of IP cores, performing structural and functional analysis, and cross-checking assumptions at both the SoC and IP levels to ensure comprehensive verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current CDC and RDC verification tools are used for SoC design, then verification can be performed at the SoC level, but assumptions at the individual IP core level are not adequately verified leading to incomplete analysis
Solution Approach 1:
The verification process is segmented into multiple hierarchical levels: IP core level verification and SoC level verification. Each level independently verifies assumptions specific to that hierarchy, with IP core level checking internal signaling and clock domain crossings within individual cores, while SoC level verifies interconnectivity and domain crossings between cores. This segmentation enables comprehensive verification without requiring a single complex verification pass.
Solution Approach 2:
The verification approach adds a hierarchical dimension to the verification process by introducing multiple levels of analysis (IP core level and SoC level). This dimensional change allows assumptions to be verified at appropriate granularity levels, transforming a flat verification process into a multi-layered verification hierarchy that captures both detailed and system-level behaviors.
2Reliability
If hierarchical verification with structural analysis is performed, then comprehensive CDC and RDC verification is achieved, but verification time and computational resources increase
Solution Approach 1:
Structural analysis of IP cores is performed as a preliminary action before formal CDC and RDC verification. This preliminary structural analysis extracts clock domains, reset domains, and signaling relationships from IP core data models, preparing verification data in advance. By performing this analysis beforehand, the actual verification process benefits from pre-processed information, reducing redundant analysis during the main verification pass.
Solution Approach 2:
The verification process applies partial verification at each hierarchical level, focusing on assumptions relevant to that specific level rather than performing complete verification of all assumptions at all levels. IP core level verification focuses on internal assumptions while SoC level verification focuses on integration assumptions, avoiding excessive verification of already-validated aspects and reducing overall verification time.
Data Source
AI summary
A method includes obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, where the IP cores include reusable units of logic for a system on a chip (SoC), and performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, where the hierarchical CDC and RDC verification includes consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use in the SoC.