FPGA Security via Extended Signal Path Runtime
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Solution Overview
Problem
FPGAs are vulnerable to unauthorized use of RTL source code, as attackers can recreate configuration files, bypassing existing protective mechanisms, and differential power analysis attacks can reveal internal processes, compromising security.
Innovation Solution
The method involves generating configuration data with synthesis conditions that extend the signal path runtime of specific logic elements beyond one clock cycle, ensuring that even if unauthorized access occurs, the FPGA will not function correctly with a conventional configuration file, by dividing logic circuits into subcircuits and allowing timeouts for specific logic elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the signal path runtime of logic elements is extended beyond one clock cycle, then security against unauthorized configuration file creation is improved, but device complexity and synthesis difficulty increase
Solution Approach 1:
The patent changes the runtime parameter of selected logic elements from the conventional one clock cycle to multiple clock cycles. This parameter modification creates a security mechanism where unauthorized synthesis tools cannot generate functional configuration files, as they assume standard one-cycle runtime. The security improvement comes from this fundamental parameter deviation without requiring complex hardware additions.
2Reliability
If synthesis conditions with timeouts are added to extend signal path runtime, then protection against differential power analysis attacks is improved, but synthesis time and tool complexity increase
Solution Approach 1:
The patent applies preliminary action by pre-defining synthesis conditions with timeout values during the synthesis phase. Selected logic elements are marked with specific runtime requirements before implementation. This allows the synthesis tool to automatically adjust signal path routing and logic element selection to meet the extended runtime requirements, preventing differential power analysis attacks without requiring manual intervention or post-synthesis modifications.
3Reliability
If logic circuits are divided into subcircuits to extend runtime, then security is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments logic circuits into multiple subcircuits that are distributed across different logic elements. This segmentation naturally extends the signal path runtime as signals must propagate through multiple stages over several clock cycles. The segmentation is achieved through synthesis conditions that specify minimum runtime requirements, causing the synthesis tool to automatically divide and distribute logic functions across multiple elements, thereby improving security without requiring manual circuit division.
Data Source
Figure 1~2
AI summary
Method for protecting an FPGA from unauthorized application of the RTL source code, wherein the FPGA consists of many logic elements (LE) that can be interconnected via a grid, wherein each logic element (LE) contains a logic circuit (L; L1, L2, L3) and a register (R1), wherein a synthesis tool generates the configuration data from the RTL source code, which is loaded into the logic circuits (L; L1, L2, L3) and the registers (R1, R2) when the FPGA's supply voltage is switched on, wherein, in addition to the RTL source code, the synthesis tool is supplied with an instruction in the form of a synthesis condition when generating the configuration data, with which at least one signal path (S) for a logic element (LE) is defined such that, during operation of the FPGA, a propagation delay on this signal path is longer than one clock cycle of the FPGA.