3D Memory Peripheral Layout for Faster Sense Amplifier Access
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing chip size and operation speed due to the layout and configuration of memory cell arrays and peripheral circuits, which affects the efficiency of read and write operations.
Innovation Solution
The semiconductor memory device is designed with a specific configuration where a sense amplifier is placed between the substrate and the memory cell array, with a second peripheral circuit having a smaller length than half that of the sense amplifier, allowing for a reduced chip size and improved operational speed by reducing the distance between bit lines and memory pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory cell array and peripheral circuits are arranged in a conventional layout, then the chip area is reduced, but the operation speed decreases due to increased distance between bit lines and memory pillars
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture where memory cell arrays are arranged in multiple planes along the vertical direction. This allows bit lines to be positioned closer to memory pillars in the vertical dimension while maintaining a compact footprint area, thereby improving operation speed without increasing chip area.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell array planes are stacked vertically within a compact chip footprint. The sense amplifier is positioned to serve multiple planes simultaneously, and peripheral circuits are integrated in a nested manner around the memory structures, achieving high density without compromising speed.
2Productivity
If multiple planes are operated independently to increase productivity, then noise interference from power supply circuits increases
Solution Approach 1:
The patent introduces power supply circuits as intermediary elements positioned between the signal lines and the memory cell arrays. These power supply circuits are strategically placed to provide power to multiple planes while being electrically isolated to minimize noise coupling, enabling independent plane operations without significant noise interference.
Solution Approach 2:
The patent applies different quality characteristics to different regions of the device. Power supply circuits are localized in specific regions with optimized electrical properties to minimize noise, while memory cell arrays in different planes are designed with local shielding and routing strategies to maintain signal integrity during independent operations.
3Reliability
If the sense amplifier size is increased to improve signal detection capability, then the chip area increases
Solution Approach 1:
The patent designs the sense amplifier to serve multiple memory cell array planes simultaneously through a shared architecture. The sense amplifier circuitry is configured to detect signals from multiple planes in sequence or parallel, reducing the need for separate sense amplifiers for each plane and thereby minimizing the total chip area while maintaining high signal detection capability.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes the following structure. A memory array is provided on a first-direction side of a substrate. The first direction intersects the substrate. The first peripheral circuit is provided between the substrate and the memory array. The second peripheral circuit is provided between the substrate and the memory array and on a second-direction side of the first peripheral circuit. The second direction intersects the first direction. The sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits. A second-direction length of the second peripheral circuit is smaller than half a second-direction length of the sense amplifier.