3D Memory Peripheral Circuits for Low Leakage and High Voltage
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Solution Overview
Problem
Existing memory devices face challenges in achieving high speed, low leakage current, high voltage, and small size in memory peripheral circuits without increasing cost, as scaling down planar transistors leads to undesirable high leakage current and advanced CMOS technology nodes are not suitable due to voltage reduction and increased complexity.
Innovation Solution
Replace conventional planar transistors in memory peripheral circuits with 3D transistors, allowing for a hybrid configuration with both 3D and planar transistors in the same process flow, which reduces leakage current and enables smaller sizes while maintaining high saturated drain current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used in memory peripheral circuits, then manufacturing process is simpler, but integration density and performance are limited
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional FinFET structures by introducing vertical fins that extend upward from the substrate. This dimensional change enables higher integration density by utilizing the third dimension (height) for transistor stacking and increased channel width, while maintaining compatibility with existing manufacturing processes through adapted fin formation techniques
2Productivity
If transistor size is reduced to increase density, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the geometric parameters of transistors by introducing vertical fins with controlled heights and widths. This parameter transformation allows achieving higher effective channel widths and densities without proportionally reducing lateral dimensions, thereby maintaining manufacturability while increasing integration density through vertical dimension optimization
3Productivity
If three-dimensional FinFET structures are implemented, then integration density and performance improve, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming isolation regions, creating fin patterns through lithography and etching, depositing gate materials, and subsequent processing steps. This segmentation of the fabrication process into manageable discrete operations simplifies the implementation of complex three-dimensional FinFET structures by breaking down the overall manufacturing into standardized, controllable steps
Data Source
Figure 1A~1B
Figure 2
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AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including a peripheral circuit, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuit includes a 3D transistor. The array of memory cells is coupled to the peripheral circuit across the bonding interface.