3D Memory Peripheral Stacking for Density and Voltage Separation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cells face density limitations and scaling challenges due to increased complexity and cost of peripheral circuits, which are not effectively addressed by traditional CMOS technology scaling, and require higher voltages not compatible with logic devices.
Innovation Solution
The peripheral circuits of 3D memory devices are stacked in different planes vertically, with memory cell arrays and peripheral circuits with varying voltage requirements fabricated separately on different substrates and bonded using hybrid or transfer bonding, allowing for independent thermal budgets and reduced planar chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional plane memory structures are used, then manufacturing process is simpler, but memory capacity and density are limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked memory structures. Multiple memory layers are stacked vertically along the channel length, enabling memory capacity to scale with the number of layers rather than just increasing chip area. This dimensional change allows significant increase in memory density without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent implements a nested structure where multiple memory layers are stacked within a single channel structure. Each memory layer contains memory cells arranged in tiers, with word lines and bit lines extending through multiple layers. This nesting approach allows multiple functional units to be integrated within a compact vertical footprint, increasing capacity without linearly increasing overall structure complexity.
2Quantity of substance
If conventional planar memory structures are used, then device fabrication is easier, but scaling to higher capacities is difficult
Solution Approach 1:
The patent employs three-dimensional vertically stacked structures where memory layers are formed along the channel length. This vertical stacking enables capacity scaling by adding layers rather than increasing lateral dimensions, thereby avoiding the need for progressively smaller feature sizes that would demand increasingly precise fabrication.
Solution Approach 2:
The memory structure is segmented into multiple discrete layers stacked vertically, with each layer containing memory cells organized in tiers. This segmentation allows independent formation and control of each layer, enabling scalable manufacturing where additional layers can be added without fundamentally changing the fabrication process for existing layers.
3Quantity of substance
If three-dimensional vertically stacked structures are implemented, then memory capacity increases, but process complexity increases
Solution Approach 1:
Multiple memory layers are nested within a single channel structure, sharing common channel regions and control gates. This nested configuration increases capacity by utilizing vertical space efficiently while avoiding the need for separate fabrication processes for each layer, thereby managing process complexity.
Solution Approach 2:
The channel structure serves multiple functions simultaneously: it acts as the conductive path for all memory cells across different layers, provides mechanical support for the stacked structure, and enables electrical control through shared control gates. This multi-functionality reduces the number of separate components that would otherwise require separate manufacturing steps.
4Quantity of substance
If memory cells are arranged in multiple tiers, then capacity density improves, but control gate complexity increases
Solution Approach 1:
Multiple control gates are merged into a single continuous control gate structure that extends through the channel length and controls multiple memory layers simultaneously. This merged control structure increases capacity by enabling multi-tier memory cells while reducing control complexity by eliminating the need for separate control gates for each layer.
Solution Approach 2:
The control gate structure performs multiple functions: it controls the potential well formation for memory cells in all tiers, provides electrical isolation between adjacent memory layers, and enables read and write operations across multiple layers through a single control interface. This multi-functionality reduces overall control structure complexity despite increased capacity.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.