3D Memory Chip Stacking with Perpendicular Gate Lines for Low Warpage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for semiconductor devices that can improve integration density and reliability for high-capacity data storage in electronic systems.
Innovation Solution
A semiconductor device is designed with a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The memory chip structures include vertically stacked gate lines and vertical memory structures penetrating through the gate lines, with the second memory chip structure in contact with the first memory chip structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally instead of two-dimensionally, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking multiple memory chip structures vertically, transitioning from two-dimensional to three-dimensional spatial utilization. This enables increased data storage capacity by adding the vertical dimension to the traditional planar memory layout, with multiple stacks of memory cells arranged in different horizontal directions within the same footprint area.
2Quantity of substance
If multiple memory chip structures are stacked vertically, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into multiple independent memory chip structures that can be manufactured separately and then stacked vertically. Each memory chip structure contains complete functional elements including gate lines, vertical memory structures, and peripheral circuits, allowing for modular manufacturing and assembly while achieving high integration density through vertical stacking.
3Quantity of substance
If gate lines are stacked in vertical direction extending in horizontal directions, then the number of gates is increased, but structural stability deteriorates due to warpage
Solution Approach 1:
The patent employs asymmetric structural design where memory chip structures with gate lines extending in different horizontal directions (first and second perpendicular directions) are alternately stacked. This asymmetric arrangement, combined with peripheral circuit structures positioned between memory chip structures, creates a balanced three-dimensional architecture that distributes stress uniformly, preventing warpage while maximizing the number of gates.
Data Source
AI summary
The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.