3D Memory Pillar Contact Structure for Stable Source-Channel Connection
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Solution Overview
Problem
The degradation of CMOS devices due to collateral thermal cycling and hydrogen diffusion during the manufacture of three-dimensional memory devices poses challenges for the performance of support circuitry in vertical NAND strings, necessitating high-performance support circuitry that is easier to implement than conventional methods.
Innovation Solution
A bonded three-dimensional memory device with a pillar contact between vertical semiconductor channels and a source layer is formed using an alternating stack of insulating and electrically conductive layers, a semiconductor material layer, and a dielectric spacer layer, where a memory opening fill structure includes a dielectric core and a vertical semiconductor channel with a hollow portion, and a source layer is directly formed on the pillar portion of the vertical semiconductor channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form support circuitry for vertical NAND strings, then the manufacturing process is well-established, but the support circuitry degrades due to collateral thermal cycling and hydrogen diffusion
Solution Approach 1:
The support circuitry is segmented into separate functional layers: a source layer formed directly on the substrate, alternating stacks of insulating and conductive layers formed thereover, and vertical semiconductor channels extending through the alternating stack. This segmentation allows each layer to be optimized independently and reduces the propagation of thermal and hydrogen damage throughout the entire structure.
Solution Approach 2:
The alternating stack of insulating layers and electrically conductive layers serves as an intermediary structure between the source layer and the vertical semiconductor channels. This intermediate structure protects the support circuitry from collateral thermal cycling and hydrogen diffusion while maintaining electrical connectivity.
2Reliability
If a pillar contact structure is formed between vertical semiconductor channels and source layer, then electrical contact reliability is improved, but the manufacturing complexity increases
Solution Approach 1:
The source layer is formed directly on the substrate before the alternating stack and vertical channels are created. This preliminary action ensures that the pillar contact structure is pre-positioned and aligned, simplifying subsequent manufacturing steps while ensuring reliable electrical contact between the vertical semiconductor channels and the source layer.
Data Source
AI summary
A memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located over the alternating stack, a dielectric spacer layer located over the semiconductor material layer, a memory opening vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located over the dielectric spacer layer and contacting the pillar portion. In one embodiment, a tubular spacer laterally surrounds the pillar portion, is laterally spaced from the pillar portion by a cylindrical portion of the memory film, and contacts a cylindrical sidewall of the semiconductor material layer.