3D Semiconductor Memory Pillar Spacing for Capacitance Reduction

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Solution Overview

Problem

There is a demand for higher levels of integration in 3-dimension stacked semiconductor memory devices, and existing technologies face challenges in increasing the distance between bit lines while maintaining device size, which affects capacitance and manufacturing costs.

Innovation Solution

The semiconductor memory device incorporates a specific structure with pillars and interconnections arranged in a matrix form, with varying distances between bit lines and plugs, allowing for increased distance between bit lines without increasing device size, and uses a manufacturing method that avoids the side wall process to reduce manufacturing costs and enhance capacitance reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the distance between bit lines is increased to reduce capacitance, then the capacitance of bit lines is reduced, but the device size increases

Engineering Contradiction:

Improvecapacitance of bit linesVSAvoiddevice size

Core Design Contradiction:

Use of energy by moving objectVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar arrangement to a three-dimensional stacked structure with pillars extending in the vertical direction. Bit lines are positioned at different heights (first bit line at first height, second bit line at second height), utilizing the vertical dimension to increase spacing while maintaining a compact footprint area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The device is divided into multiple stacked layers with pillars segmented at different heights. The first pillar extends to a first height with a first bit line, while the second pillar extends to a greater second height with a second bit line. This segmentation allows independent positioning of bit lines in the vertical dimension.

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If the distance between bit lines is increased to reduce capacitance, then the capacitance of bit lines is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improvecapacitance of bit linesVSAvoidmanufacturing complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The manufacturing process is divided into sequential steps: forming the first pillar to a first height, then forming the second pillar to a greater second height. This segmented approach simplifies manufacturing compared to creating complex three-dimensional structures in a single process, as each pillar can be formed using standard semiconductor fabrication techniques.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9947683B2Three-dimensional semiconductor memory device and method for manufacturing the same

Publication Date: 2018.04.17 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second interconnection, a third interconnection, and a fourth interconnection. The first to fourth pillars are provided within the structural body extending along the first direction. A first distance between the first pillar and the first interconnection is greater than a second distance between the third pillar and the third interconnection. The first distance is greater than a third distance between the fourth pillar and the fourth interconnection. A fourth distance between the second pillar and the second interconnection is greater than the second distance. The fourth distance is greater than the third distance.