3D Memory Bit-Line Pillars for Wire Delay and Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits (ICs) scale down, wire performance and power consumption become dominant issues due to increased wire lengths and complexity, which traditional 2D designs cannot effectively address, necessitating innovative 3D stacking techniques to improve transistor density and reduce wiring delays.
Innovation Solution
The development of 3D Integrated Circuit (IC) devices and fabrication methods that enable layer transfer and reuse of donor wafers, incorporating vertically oriented bit-line pillars connected to memory transistors with specific geometries and materials, such as metalized sources and drains, and crystallized polysilicon channels, to enhance memory cell performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 2D IC design is used, then manufacturing process is simpler, but wire length increases and performance degrades
Solution Approach 1:
The patent transitions from traditional 2D IC layout to 3D stacked architecture, where memory cells are arranged in vertical layers with bit-line pillars extending through multiple levels. This dimensional change reduces wire lengths by placing transistors closer to their interconnects in the vertical dimension, thereby improving wire performance and signal speed while maintaining manufacturing feasibility through established CMOS processes.
2Productivity
If component size is scaled down, then transistor density improves, but wire performance degrades
Solution Approach 1:
By stacking memory cells vertically in multiple layers connected by bit-line pillars, the invention achieves high transistor density without proportionally increasing wire lengths. The vertical arrangement allows transistors in upper layers to connect to bit lines through short vertical pillars rather than long lateral wires, thus maintaining wire performance while scaling up transistor density.
Solution Approach 2:
The patent employs different structural configurations for different parts of the memory array, such as varying pillar heights, channel orientations, and material compositions across layers. This local optimization allows each region to be tuned for its specific performance requirements, balancing density and wire performance across the entire 3D structure.
3Adaptability or versatility
If wire length increases, then IC functionality expands, but power consumption increases
Solution Approach 1:
The 3D stacked architecture with vertical bit-line pillars enables complex memory functionality across multiple layers while keeping interconnect lengths short. The vertical stacking allows functional expansion through layer multiplication rather than lateral wire extension, thereby maintaining lower power consumption despite increased IC capability.
Data Source
AI summary
A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.