3D Memory Plane Separation Blocks for Dense Vertical Stacking
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Solution Overview
Problem
As feature sizes of planar semiconductor devices approach their limits, traditional fabrication techniques become challenging and costly, necessitating a shift to three-dimensional (3D) semiconductor device architectures to enhance density and efficiency.
Innovation Solution
A 3D memory device design featuring multiple memory planes separated by a dielectric stack with interleaved conductive and dielectric layers, including channel structures and slit structures, which allows for vertical stacking and improved electrical isolation, enabling increased storage capacity per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar semiconductor devices are scaled to smaller sizes, then storage density is improved, but fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) semiconductor devices to three-dimensional (3D) stacked memory architecture. Multiple memory planes are stacked vertically with separation blocks between them, enabling increased storage density without further scaling feature sizes. This dimensional change allows continued density improvement while avoiding the fabrication challenges of extreme miniaturization.
2Quantity of substance
If multiple memory planes are stacked vertically, then storage capacity is improved, but electrical isolation between planes becomes difficult
Solution Approach 1:
The patent divides the stacked memory structure into separate memory planes with distinct separation blocks between adjacent planes. Each separation block contains interleaved dielectric layers that segment and electrically isolate the conductive layers of different memory planes, ensuring reliable electrical isolation while maintaining the high-density 3D architecture.
Solution Approach 2:
The separation blocks utilize composite structures with interleaved dielectric layers (first and second dielectric layers) that provide enhanced electrical isolation. This composite material approach creates effective barriers between adjacent memory planes, enabling reliable vertical stacking with maintained electrical isolation.
3Quantity of substance
If feature sizes are reduced, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
By moving to 3D stacking architecture, the patent achieves higher device density through vertical integration rather than further lateral scaling. This allows density improvement while maintaining larger, more controllable feature sizes in the lateral dimensions, thereby reducing manufacturing precision requirements.
4Manufacturing precision
If separation blocks include dummy channel structures, then etching uniformity is improved, but device complexity increases
Solution Approach 1:
Dummy channel structures are introduced as intermediary elements within the separation blocks. These dummy structures serve as placeholders that maintain etching uniformity across the wafer by providing consistent etch targets, while the interleaved dielectric layer structure manages the added complexity through systematic layering.
Data Source
AI summary
A three-dimensional (3D) memory device includes a plurality of memory planes and a separation block. Each memory plane includes a plurality of memory blocks. Each memory block includes a memory stack including interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending through the memory stack. The separation block extending laterally to separate each two adjacent memory planes. Each separation block includes a dielectric stack including interleaved second dielectric layers and the first dielectric layers. The first dielectric layers extend across the memory blocks and the separation block, and the second dielectric layers separate the conductive layers of two adjacent memory blocks.