3D Memory Stack Power Channels for Voltage Drop Reduction
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Solution Overview
Problem
Three-dimensional (3D) memory devices experience significant power consumption and voltage drops due to high wiring resistance, leading to unstable operations, especially at upper layers where multiple circuits are activated simultaneously.
Innovation Solution
The implementation of additional power supply wirings and power supply through electrodes that are modeled as resistors, providing multiple electrical paths to reduce wiring resistance and stabilize operations by distributing power supply voltage effectively across the 3D memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple circuits are activated simultaneously to achieve high transfer rates and wide bandwidth buses, then productivity and data transfer speed are improved, but power consumption increases and voltage drops occur due to high wiring resistance
Solution Approach 1:
The patent segments the memory device into multiple independent stacks, each with its own power supply wiring. This allows different stacks to operate independently with different power consumption levels, enabling high transfer rates in active stacks while reducing overall power consumption by keeping other stacks in lower-power states.
Solution Approach 2:
The patent implements dynamic power management where power supply to different stacks can be independently controlled and adjusted based on operational requirements. This allows the system to optimize between high performance (all stacks active) and low power consumption (selective stacking activation) in real-time.
2Productivity
If multiple circuits are activated simultaneously to achieve high transfer rates, then productivity is improved, but voltage drops occur due to high wiring resistance causing unstable operations
Solution Approach 1:
By dividing the memory device into multiple stacks with separate power supply wirings, the patent reduces the current load on each individual wiring path. This segmentation of power distribution reduces voltage drops in each wiring and improves operational stability while maintaining high overall data transfer rates.
Solution Approach 2:
The patent introduces intermediate power supply structures within each stack that act as local power distribution points. These intermediaries reduce the effective wiring length and resistance between the power source and individual circuits, thereby reducing voltage drops and improving operational reliability.
3Area of stationary object
If a large number of vertical vias are used to interconnect stacked dies, then chip size is reduced and bandwidth is increased, but wiring resistance increases causing voltage drops
Solution Approach 1:
The patent segments the vertical interconnection structure into multiple stacks, each with its own dedicated power supply vias and wiring. This reduces the current density in each via and wiring path, thereby reducing resistive power loss while maintaining the high-density 3D stacked architecture and small chip footprint.
Solution Approach 2:
The patent implements local power supply structures within each stack, providing power closer to the consuming circuits. This local quality improvement reduces the wiring length and resistance in critical paths, minimizing voltage drops while maintaining the compact 3D structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the resistance between power supply sources and circuitry ends, thereby minimizing voltage drops and ensuring stable operations in 3D memory devices by distributing power supply voltage efficiently across the device.
Implementation Method 1
The implementation of additional power supply wirings and power supply through electrodes that are modeled as resistors, providing multiple electrical paths to reduce wiring resistance
Data Source
AI summary
Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.