3D Memory Cell String Layout With Prism Insulator and Charge Trapping
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Solution Overview
Problem
Current semiconductor devices face limitations in integration density, storage capacity, retention period, and electrical characteristics, particularly in three-dimensional memory cell arrangements, which hinder the development of high-capacity, reliable, and efficient memory solutions.
Innovation Solution
A semiconductor device with a prism-like insulator and multiple transistors connected in series, utilizing an oxide semiconductor with indium, aluminum, gallium, yttrium, or tin, and zinc, where the charge accumulation layer is positioned between insulators, enabling a three-dimensional memory cell arrangement with improved integration and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional memory cell arrangement is used, then manufacturing is easier, but integration density reaches limits
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple memory cell strings vertically over a single substrate. Multiple memory cell strings are formed in the vertical direction, allowing integration density to increase while maintaining manufacturing feasibility through standardized layer-by-layer fabrication processes.
2Productivity
If three-dimensional memory cell arrangement is implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The memory device is segmented into multiple independent memory cell strings, each comprising a series of memory cells with their own gate electrodes, gate insulators, and semiconductor layers. This segmentation allows complex three-dimensional functionality to be achieved through repetition of standardized modular units, reducing overall device complexity.
Solution Approach 2:
Multiple memory cell strings are nested vertically over the substrate, with each memory cell string containing nested layers of gate electrodes, gate insulators, and semiconductor layers. This nested structure achieves high integration density while maintaining organized, manageable complexity through hierarchical arrangement.
3Ease of manufacture
If conventional transistors are used, then manufacturing is simpler, but leakage current is higher
Solution Approach 1:
The gate insulator is constructed as a composite structure comprising a first insulator layer and a second insulator layer with different material compositions and dielectric constants. This composite insulator structure reduces leakage current through the tunneling barrier while maintaining manufacturability through sequential deposition processes. The charge accumulation layer is positioned within this composite insulator structure to optimize electrical characteristics.
4Ease of manufacture
If conventional gate insulator structure is used, then manufacturing is easier, but subthreshold swing is larger
Solution Approach 1:
The gate insulator structure exhibits local quality variations with different insulator materials positioned at specific locations within the insulator stack. The first insulator and second insulator have different dielectric properties optimized for their respective positions, with the charge accumulation layer strategically positioned within the composite structure to achieve small subthreshold swing values while maintaining ease of manufacture through standard semiconductor fabrication techniques.
Data Source
AI summary
A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.