Solid-State Devices TRIZ Cases

A non-uniform insulating film keeps adjacent micro light-emitting elements apart, reducing short-circuits and preserving emission stability.

Non-uniform electrode spacing evens the electric field, improving light-emitting element alignment and pixel emission uniformity.

An auxiliary electrode nested within the pixel defining layer cuts cathode resistance and voltage drop for more uniform top-emitting OLED brightness.

Through-vias and stacked circuit layers cut image sensor terminal footprint while maintaining reliable signal input and output.

Near-field light generated by a two-stage control member boosts one polarization component, improving emission efficiency for display optics.

A transparent substrate with lattice-like micropores guides light through a front thin layer, improving emission visibility while cutting light loss.

Optimized gate and dummy gate end-cap spacing lets same-height standard cells of different widths share one routing block without overlap or current-control loss.

Alternating wiring groups are rearranged to enlarge blank areas in the camera region, improving light transmittance and imaging quality.

A blocking part with an etching opening forms dual film-layer trenches in one etch, cutting OLED panel bend-area mask steps and cost.

Variable spacing and offset between power semiconductor devices reduce thermal crowding, improve thermal balance, and raise module power density.

Unified metal select gates, high-k dielectrics, and ONO storage help embedded flash balance fast logic CMOS with reliable memory cells.

Parallel first and second active layers with separate gates improve oxide TFT mobility while enabling tighter thickness control and better uniformity.

A nucleation-inhibiting coating blocks unwanted conductive deposition, improving OLED patterning accuracy while reducing debris and yield loss.

An aluminum and tungsten oxide electrode stack cuts contact resistance and RC delay while protecting the aluminum layer from corrosion.

A top protective layer enables full sidewall reflective coating on LED chips, simplifying fabrication while reducing light leakage and crosstalk.

Spacers and magnet focusing units reshape the field to orient display LED chips accurately, raising assembly rate and reducing residual chips.

A suspended TFT forms an electrostatic storage capacitor that protects display signal lines without adding line load or harming yield.

Different mesa porosity levels replace localized dopant implantation, simplifying epitaxy of GaN-based diode arrays with varied wavelengths.

Patterned InGaN mesas enable aligned native RGB micro-LED growth in one epitaxy flow, avoiding pick-and-place and quantum dot deposition limits.

Predetermined carrier remapping mixes categorized Micro LED groups to reduce wavelength, brightness, and chromaticity variation across displays.

Using a transparent storage capacitor plate expands the non-opaque pixel region and improves aperture ratio without reducing capacitor area.

A functional interlayer improves photoresist adhesion during etching while preserving the darkening layer’s low-reflectivity effect.

Monolithic III-nitride LED arrays use tunnel junctions and etch stop layers to avoid pick-and-place, simplify contacts, and lower voltage.

Redirects 0°-40° incident light to near-normal entry, improving small-pixel brightness, uniformity, and shading control.

A prism-like insulator and stacked memory cell strings raise 3D memory density while improving retention, leakage, and subthreshold swing.

Additional edge seals and a via bar close seal-ring gaps in hybrid-bonded packages, limiting moisture ingress and improving bond reliability.

A doped intermediate semiconductor layer redirects carriers away from the avalanche region, reducing SPAD after-pulses and improving detection accuracy.

A non-magnetic insertion layer blocks Ti and N diffusion during annealing, preserving perpendicular magnetic anisotropy and junction shape control.

Horizontally arranged LED units cut display mounting time, avoid stacking-sequence limits, and simplify repair of defective emitters.

Integrated ESD protection on a transparent unit-pixel substrate shields micro LEDs from discharge and handling damage during mounting.

A matrix-attached micro LED and transistor structure cuts one-by-one mounting time, enabling thinner high-resolution displays with better yield.

Non-conductive isolation structures and direct electrode contact suppress pixel cross-talk, enabling smaller image sensor pixels without added complexity.

A perimeter black mask strip on an image sensor cover reduces adhesive shadowing, improves curing uniformity, and lowers bond pad corrosion risk.

An optical-film-integrated microlens array improves light condensing, cuts reflection loss and shading, and supports better autofocus imaging.

Groove-type discharge paths guide metal bonding solvent for uniform flow and more accurate LED transfer on large-area display substrates.

Electrical insulation inside the epitaxial layer forces SCR current through the substrate, raising holding voltage and reducing unintended ESD triggering.

A vanadium-aluminum wiring stack preserves conductivity during laser curing by forming a detour path when the aluminum layer partially melts.

A perforated two-layer metal shield protects the gate driver from static electricity while releasing heat to reduce peeling during deposition.

Vertical word lines and power rails let stacked SRAM bit cells keep identical layouts, boosting 3D interconnect density without metal crossings.

Electrical insulation in the epitaxial layer forces current through the substrate, raising SCR holding voltage and reducing unintended ESD triggering.

Rate alignment logic matches slower memory core output to faster link bandwidth, enabling continuous transfer and avoiding resource conflicts.

Series or vertically stacked photovoltaic cells create multiple voltage outputs in a small footprint, removing the need for IoT voltage converters.

A sub-trench with thermal oxide localizes crystal defects in the guard ring and blocks dislocation spread into circuit regions.

Disconnected gate-line sub-traces linked by transfer electrodes curb charge buildup, preventing arcing and breakage during array substrate manufacturing.

Cyclic gallium-oxygen pretreatment and ALD III-V channel deposition improve adhesion and conductivity in scaled V-NAND memory.

A stepped pad with a protruding section lets solder balls self-position around the pad, improving stability and preventing shorts in thin stacked chips.

Stacked and folded ferroelectric capacitors cut effective field, delay refresh, and improve bit-cell endurance in low-power memory.

A bent rigid-flex wiring board separates stacked chips from the image sensor, limiting heat transfer while keeping the endoscope module compact.

A grounded intermediary electrode isolates stacked memory cells from control circuits to prevent arcing, limit parasitic capacitance, and stabilize operation.

A thin-film flip-chip mesa uses sidewall contacts and dielectric isolation to preserve light-emitting area as micro-LED pixels shrink.