Array Substrate Etch-Blocking Pattern for Pixel Electrode Defects
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Solution Overview
Problem
The manufacturing process of array substrates for liquid crystal display devices faces defects in electrical connections due to improper etching times during the formation of pixel electrodes, leading to issues with the rift section and exposure of common electrode lines.
Innovation Solution
Incorporating an etch-blocking pattern in the peripheral area of the pixel electrode within the overlapping region between the pixel electrode and the first metal layer, which helps in preventing defects by improving the lifting-off process and reducing the risk of electrical connection failures during the third patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the first and second insulating layers are over-etched with a dry method to form a rift section of the pixel electrode layer, then the lifting-off process can be assured to work, but the common electrode line under the gate insulating layer may be exposed, leading to defects in the electrical connection between the pixel electrode and the common electrode line
Solution Approach 1:
An etch-blocking pattern is introduced as an intermediary element between the pixel electrode and the common electrode line. This pattern prevents the etching process from exposing the common electrode line while still allowing the formation of the rift section, thus mediating between the conflicting requirements of manufacturing precision and electrical connection reliability
Solution Approach 2:
The etch-blocking pattern is formed in advance to prevent the harmful effect of over-etching. By placing this protective pattern before the etching process, the patent preemptively blocks the potential damage to the common electrode line, ensuring electrical connection reliability while maintaining the ability to form the rift section
Data Source
AI summary
The present invention provides an array substrate comprising: a substrate, having a thin film transistor (TFT) formed thereupon, the TFT having a gate electrode, a source electrode and a drain electrode; a first metal layer, formed on the substrate, and comprising a gate line and the gate electrode of the TFT; a first insulating layer, covering the first metal layer and the substrate; a semiconductor layer, an ohmic contact layer, and a second metal layer, which are sequentially formed on the first insulating layer; a second insulating layer, covering the semiconductor layer, the ohmic contact layer, and the second metal layer; a pixel electrode, provided on the second insulating layer and is connected to the drain electrode. The second metal layer further comprises an etch-blocking pattern in the peripheral area of the pixel electrode within the overlapping region between the pixel electrode and the first metal layer.