Stacked Folded Ferroelectric Bit-Cell Layout for Charge Disturbance
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Solution Overview
Problem
Conventional non-volatile memories, such as MRAM and flash memories, are not suitable for low-power and compact computing devices due to high write energy, low density, and high power consumption, and traditional ferroelectric memories suffer from charge degradation and disturbance issues.
Innovation Solution
The use of stacked and folded capacitor configurations in memory bit-cells, combined with word-line boosting and refresh mechanisms, to mitigate charge disturbance and enhance memory endurance, allowing for efficient data retention and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memories (MRAM, flash) are used, then data retention is achieved, but write energy consumption is high and density is low
Solution Approach 1:
The patent employs ferroelectric materials with specific phase transitions and polarization characteristics to enable low-energy writing. By utilizing the ferroelectric hysteresis loop properties and coercive field characteristics, the memory achieves stable data retention with significantly reduced write energy compared to conventional non-volatile memories.
Solution Approach 2:
The patent uses composite capacitor structures combining ferroelectric layers with conductive oxide electrodes and tunnel barriers. This composite approach enables both low-energy operation and high-density integration by leveraging the complementary properties of different materials: ferroelectricity for non-volatility, conductive oxides for electrode functionality, and tunnel barriers for charge confinement.
2Reliability
If conventional non-volatile memories are used, then data retention is achieved, but memory density is low
Solution Approach 1:
The patent transitions from planar capacitor geometries to vertically stacked three-dimensional capacitor structures. By stacking multiple capacitor layers in the vertical dimension, the memory achieves higher density without compromising the bit-cell area, effectively utilizing the third dimension to increase storage capacity per unit area.
Solution Approach 2:
The patent implements nested capacitor configurations where capacitors are arranged in stacked and folded patterns within the bit-cell structure. Multiple capacitor elements are nested within a compact footprint, with shared electrodes and interleaved arrangements that maximize space utilization and increase effective storage density.
3Reliability
If ferroelectric memories are used, then non-volatile storage is achieved, but charge disturbance and degradation issues occur
Solution Approach 1:
The patent implements refresh mechanisms and error correction codes that proactively detect and correct charge degradation before it leads to data errors. By periodically refreshing ferroelectric capacitors and using ECC to compensate for bit failures, the system cushions against the inherent charge disturbance and degradation characteristics of ferroelectric materials.
Solution Approach 2:
The patent employs feedback-based read-disturb mitigation techniques where read operations are optimized to minimize perturbation of stored charge. By sensing voltage changes during read operations and adjusting subsequent write and refresh operations accordingly, the system feedback-controls the impact of reads on charge stability, reducing cumulative disturbance effects.
4Reliability
If multiple capacitors are used in memory bit-cells, then memory gain and endurance are improved, but area occupation increases
Solution Approach 1:
The patent merges multiple capacitor structures by sharing common electrodes and interleaving capacitor elements within the same bit-cell. Multiple capacitors are combined in a compact arrangement where top and bottom electrodes are shared or adjacent, reducing the total area required compared to discrete capacitor implementations while maintaining the multi-capacitor gain mechanism.
Solution Approach 2:
The patent nests multiple capacitor elements within a compact stacked configuration, placing capacitors in vertical and horizontal arrangements that maximize space utilization. The nested layout allows multiple capacitors to occupy overlapping or adjacent spatial regions, effectively increasing capacitor density within the bit-cell footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the effective field across ferroelectric capacitors, delays the need for refreshing, and improves memory endurance by minimizing charge disturbance, making non-volatile memories more suitable for low-power devices.
Implementation Method 1
an individual memory bit-cell includes one transistor and multiple ferroelectric capacitors
Implementation Method 2
This configuration reduces the effective field across ferroelectric capacitors, delays the need for refreshing, and improves memory endurance by minimizing charge disturbance
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.