Shift Register LUT Cell-by-Cell Reprogramming in SRAM FPGAs
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Solution Overview
Problem
SRAM-based FPGAs face inefficiencies in programming operations due to non-bit-addressable SRAM cells, requiring reconfiguration of multiple frames or columns, which is time-consuming and resource-intensive, especially during partial reconfiguration.
Innovation Solution
The introduction of a data write path port, reset port, and shift enable port on memory cells of SRLs allows for cell-by-cell programming, eliminating the need to reprogram multiple frames or columns, thereby simplifying state management and increasing load/store efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple frames or columns of SRAM memory cells are reprogrammed during partial reconfiguration, then the FPGA can be reconfigured, but the programming operation becomes time-consuming and resource-intensive
Solution Approach 1:
The patent segments the SRAM configuration memory into individually addressable columns, allowing selective reconfiguration of specific columns rather than requiring reprogramming of multiple frames or columns. This column-by-column addressing enables precise control over which portions of the FPGA are reconfigured, reducing the scope of programming operations during partial reconfiguration.
Solution Approach 2:
The patent implements local quality by enabling reconfiguration of specific columns within the SRAM array while leaving other columns unchanged. The column-select signals allow different columns to have different reconfiguration states, permitting localized changes to the FPGA logic fabric without affecting the entire device or requiring reprogramming of multiple frames.
2Adaptability or versatility
If multiple frames or columns of SRAM memory cells are reprogrammed during partial reconfiguration, then the FPGA can be reconfigured, but resource requirements increase
Solution Approach 1:
By segmenting the configuration memory into individually addressable columns with independent control, the patent reduces the quantity of resources required for reconfiguration. Only the specific columns needing change are accessed and reprogrammed, rather than allocating resources to reprogram entire frames or multiple columns simultaneously.
Solution Approach 2:
The patent applies partial action by reconfiguring only the necessary columns rather than performing complete frame reconfiguration. This selective approach reduces the quantity of configuration data that must be loaded and processed, decreasing resource requirements for buffer memory, data paths, and control logic during partial reconfiguration operations.
3Ease of manufacture
If traditional SRAM configuration memory is used, then the FPGA can be configured, but formatting, deformatting, and address translation are required
Solution Approach 1:
The patent segments the configuration memory into columns with individual addressing, eliminating the need for complex formatting and deformatting operations. Each column can be directly accessed and programmed with configuration data in a standardized format, removing the need for frame-based formatting and address translation layers that complicate the configuration process.
Solution Approach 2:
The patent eliminates intermediary formatting and address translation layers by implementing direct column addressing. The configuration data can be written directly to the target column without requiring formatting conversions or address translation through multiple levels of abstraction, simplifying the configuration process and reducing device complexity.
Data Source
AI summary
An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.