Logic Region Register Bypass Paths for Faster FPGA Pipelining
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Solution Overview
Problem
Conventional programmable integrated circuits face performance limitations due to increased critical path delay caused by conventional register pipelining, which introduces additional delay and reduces the number of available input terminals for custom functions.
Innovation Solution
The integration of logic regions with global interconnects, input and output selection circuitry, and bypass paths that allow direct access to registers, reducing signal delay and increasing configuration flexibility by bypassing input and output selection circuitry, thereby optimizing clock frequency and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If signals are routed through conventional programmable logic circuits for pipelining, then critical path delay is reduced, but additional delay is introduced and performance benefits are reduced
Solution Approach 1:
The circuit is segmented into conventional logic regions and accelerated logic regions with bypass paths. Pipeline registers are strategically placed in different segments: some in conventional regions (causing delay) and some in accelerated regions (providing direct bypass access). This segmentation allows selective use of pipelining benefits while avoiding unnecessary delays.
Solution Approach 2:
Accelerated logic regions act as intermediaries between conventional logic regions. These intermediate regions provide direct bypass paths that shortcut the conventional input multiplexer and look-up table circuitry, enabling fast register-to-register communication without going through the full conventional logic path.
2Adaptability or versatility
If conventional input multiplexers are used to route signals to programmable logic circuits, then routing flexibility is maintained, but signal selection time increases and performance is reduced
Solution Approach 1:
The routing path is segmented into conventional routing (through input multiplexers) and accelerated routing (through bypass paths). The bypass paths provide dedicated, hardwired connections that eliminate multiplexer selection delay for specific signal paths, while conventional multiplexers remain available for other routing needs.
Solution Approach 2:
Different quality levels of signal paths are provided: standard paths through input multiplexers for general routing flexibility, and high-speed bypass paths for critical timing paths. The bypass paths have optimized characteristics (direct connection, no multiplexer delay) specifically for paths requiring maximum speed.
3Extent of automation
If signals occupy input terminals of programmable logic circuits for pipelining, then register pipelining is achieved, but the number of available input terminals for custom user functions is reduced
Solution Approach 1:
Input terminals are segmented into those served by conventional input multiplexers and those served by accelerated bypass paths. The bypass paths provide additional dedicated input paths that do not compete with the conventional input terminals, effectively increasing the total number of available input paths for both pipelining and custom functions.
4Productivity
If clock frequency is increased to improve performance, then system performance improves, but maximum clock frequency is limited by critical path delay
Solution Approach 1:
The clocking system is segmented to provide different clocking strategies for different regions: conventional clocking for standard logic paths and accelerated clocking for bypass paths. The bypass paths are designed with shorter, optimized routing that reduces delay, allowing these paths to operate at higher clock frequencies.
Solution Approach 2:
The physical parameters of the bypass paths are optimized: shorter interconnect lengths, direct routing without multiplexers, and minimized logic stages. These parameter changes reduce the critical path delay, enabling higher clock frequencies to be achieved.
Data Source
AI summary
Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The programmable logic regions may have input selection circuitry for selecting and providing input signals from the interconnects to the programmable logic regions. The programmable logic regions may include look-up table circuitry for processing the input signals and registers for storing output signals from the look-up table circuitry. The programmable logic regions may include output selection circuitry for selecting which output signals are provided to output circuitry of the programmable logic regions. The programmable logic regions may include bypass paths that provide direct access to the registers from the interconnects by bypassing the input and output selection circuitry. Computer-aided design tools may be used to identify registers in a design that should be used for register pipelining.