Through-Die Via FPGA Interface for Backside Die Stacking
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Solution Overview
Problem
Existing die stacking techniques for FPGAs are incompatible with flip-chip packaging due to bump contacts on the face side of the FPGA die, limiting the ability to mount additional ICs.
Innovation Solution
The integration of through-die vias (TDVs) on the backside of the FPGA die allows for the stacking of additional ICs by providing an interface that couples logic elements to conductive interconnects, enabling communication between stacked ICs without disrupting the flip-chip packaging configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a second die is mounted on the face side of the FPGA die to enable die stacking, then interconnection between stacked ICs is achieved, but compatibility with flip-chip packaging is lost due to bump contacts on the face side
Solution Approach 1:
Instead of mounting the second die on the face side of the FPGA (conventional approach), the patent inverts the approach by mounting the second die on the backside of the FPGA die. This inversion allows the face side to maintain its flip-chip bump contacts for packaging compatibility, while the backside provides the mounting surface for die stacking through through-die vias that pass through the entire FPGA die thickness.
Solution Approach 2:
The patent transitions from two-dimensional face-side mounting to three-dimensional backside mounting by utilizing through-die vias that extend vertically through the FPGA die. This dimensional change allows simultaneous access to both the face side (for flip-chip packaging) and the backside (for die stacking), resolving the contradiction between interconnection capability and packaging compatibility.
2Adaptability or versatility
If bump contacts are distributed throughout the face side for flip-chip packaging, then packaging compatibility is maintained, but the ability to mount a second IC to the face side is eliminated
Solution Approach 1:
The patent segments the FPGA die into two functional surfaces: the face side dedicated to flip-chip packaging with bump contacts, and the backside dedicated to die stacking with through-die via contacts. This segmentation allows each side to independently fulfill its specific function without interfering with the other, maintaining both packaging compatibility and interconnection capability.
Solution Approach 2:
The through-die vias act as intermediaries that transfer signals and power from the backside contacts to the internal logic elements of the FPGA. This intermediary structure enables the backside-mounted second die to communicate with the FPGA logic without requiring face-side contacts, thus preserving flip-chip packaging compatibility while enabling die stacking interconnection.
Data Source
AI summary
An integrated circuit with a through-die via (TDV) interface for die stacking is described. One aspect of the invention relates to an integrated circuit die having an array of tiles arranged in columns. The integrated circuit die includes at least one interface tile. Each interface tile includes a logic element, contacts, and through die vias (TDVs). The logic element is coupled to a routing fabric of the integrated circuit die. The contacts are configured to be coupled to conductive interconnect of another integrated circuit die attached to the backside of the integrated circuit die. The TDVs are configured to couple the logic element to the contacts.