CMOS SRAM Cell With Localized SOI PMOS for Latch-Up Immunity
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Solution Overview
Problem
Current CMOS SRAM structures face challenges in reducing the area occupied by SRAM cells as technology nodes shrink, leading to increased latch-up issues and inefficiencies in processing density, with conventional designs requiring larger distances between NMOS and PMOS transistors to prevent latch-up, which in turn increases the overall SRAM cell size.
Innovation Solution
The proposed solution involves forming PMOS transistors in a localized Silicon On Insulator (SOI) structure within the same Bulk semiconductor substrate, eliminating the need for additional latch-up distance and allowing for a more compact SRAM cell design by using shallow trench isolation and underground insulating layers to isolate the PMOS transistors from the Bulk substrate, while maintaining the NMOS transistors in the Bulk substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional Bulk CMOS SRAM structure is used, then manufacturing process is simple, but latch-up issues occur and require larger distance between NMOS and PMOS transistors
Solution Approach 1:
The patent divides the substrate into two distinct regions: a Bulk region for NMOS transistors and a localized SOI region for PMOS transistors. This segmentation allows each transistor type to operate in its optimal electrical environment, preventing latch-up while maintaining manufacturing simplicity through selective region processing.
Solution Approach 2:
The patent applies different substrate qualities to different locations: Bulk substrate for NMOS devices and SOI substrate for PMOS devices. This local quality differentiation enables NMOS transistors to benefit from Bulk substrate characteristics while PMOS transistors gain latch-up immunity from SOI structure, without requiring increased spacing between devices.
2Reliability
If larger distance is reserved between NMOS and PMOS transistors to prevent latch-up, then latch-up immunity improves, but SRAM cell area increases
Solution Approach 1:
By segmenting the substrate into Bulk and SOI regions, the patent eliminates the need for large spacing between NMOS and PMOS transistors. The physical separation of transistor types into different substrate regions provides inherent latch-up prevention without consuming additional cell area.
Solution Approach 2:
The patent transitions from a planar layout approach (increasing lateral distance between transistors) to a vertical/dimensional approach by creating localized SOI regions within the substrate. This allows PMOS transistors to be isolated in three-dimensional space through the insulating layer, achieving latch-up immunity without increasing the two-dimensional cell footprint.
3Area of stationary object
If technology node is scaled down to reduce SRAM cell area, then area occupancy decreases, but latch-up issues increase and FOM increases
Solution Approach 1:
The patent applies local quality by creating SOI regions specifically where PMOS transistors are located, even as technology nodes scale down. This localized application of SOI structure provides latch-up immunity at scaled dimensions without requiring proportional increases in cell area or spacing.
Solution Approach 2:
The patent changes the substrate parameter (from Bulk to SOI) in the PMOS region to fundamentally alter the electrical characteristics and prevent latch-up. This parameter change allows scaled-down device dimensions while maintaining reliability, as the SOI structure's electrical isolation properties remain effective at smaller scales.
Data Source
AI summary
A CMOS SRAM structure includes a Bulk semiconductor substrate with a PMOS active region and an NMOS active region. A set of PMOS transistors are formed in the PMOS active region and a set of NMOS transistors are formed in the NMOS active region. A VDD contacting line is electrically coupled to the set of PMOS transistors, a VSS contacting line is electrically coupled to the set of NMOS transistors, a word line is electrically coupled to the set of NMOS transistors, a bit line is electrically coupled to the set of NMOS transistors, and a complementary bit line is electrically coupled to the set of NMOS transistors. Wherein either the PMOS active region or the NMOS active region is a SOI region which is fully isolated from a rest portion of the Bulk semiconductor substrate which does not include the PMOS active region and the NMOS active region.