Interconnect Selection Circuitry for Dense FPGA Signal Routing
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Solution Overview
Problem
Conventional programmable integrated circuits face inefficiencies due to the direct correspondence between multiplexing circuits, drivers, and interconnects, leading to wasteful resource usage and increased area occupation, particularly with varying interconnect types having different physical characteristics.
Innovation Solution
The implementation of output selection and driver circuitry with multiple selection stages, including multiplexers and tristate drivers, allows for flexible routing of signals to various interconnects, reducing the need for extensive routing paths and optimizing resource utilization by selectively driving interconnects based on their characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a direct correspondence between multiplexing circuits, drivers, and interconnects is used, then routing is simplified, but area occupation increases and resource utilization decreases
Solution Approach 1:
The patent applies universality by enabling a single multiplexing circuit to serve multiple interconnect types through the shared interconnect pool. Instead of having dedicated multiplexing circuits for each interconnect type, the system allows one multiplexing circuit to dynamically route signals to any available interconnect in the pool, making the multiplexing resource universal and multi-functional.
Solution Approach 2:
The patent merges multiple interconnect types into a single shared interconnect pool. Rather than maintaining separate routing paths for different interconnect types, the system combines them into one pool that can be dynamically allocated, reducing the total number of routing paths and associated area occupation.
2Reliability
If separate multiplexing circuits and drivers are provided for each interconnect type, then signal routing is ensured, but resource utilization becomes inefficient
Solution Approach 1:
The system enhances adaptability by making multiplexing circuits and drivers universal resources that can be dynamically allocated to different interconnect types based on demand. This allows the same hardware resources to adapt to various routing scenarios, improving resource utilization while maintaining reliable signal routing through dynamic configuration.
Solution Approach 2:
The patent introduces dynamics by enabling runtime configuration of the interconnect pool allocation. The system can dynamically adjust which interconnects are assigned to which logic circuits based on current routing requirements, rather than having fixed assignments. This dynamic allocation improves resource utilization efficiency while ensuring reliable signal routing.
3Reliability
If routing paths are provided to each multiplexing circuit, then signal delivery is guaranteed, but area occupation increases significantly
Solution Approach 1:
The patent merges multiple dedicated routing paths into a shared routing infrastructure that serves the entire interconnect pool. Instead of providing separate routing paths from logic circuits to each multiplexing circuit, the system creates shared routing paths that can be dynamically allocated to serve multiple interconnects, significantly reducing area occupation while maintaining signal delivery reliability.
Solution Approach 2:
The system segments the routing function into two parts: shared routing paths that deliver signals to the interconnect pool, and dynamic allocation logic that assigns signals to specific interconnects. This segmentation allows the routing infrastructure to be shared across multiple destinations, reducing redundant routing paths and associated area occupation.
Data Source
AI summary
Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.