3D SRAM Bit Cell Layout With Vertical Word Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D IC fabrication techniques face challenges in achieving high interconnection density and cost-effectiveness due to physical design constraints, particularly in implementing SRAM bit cells within the 3D Nanofabric design, which requires identical layouts and avoids metal crossings.
Innovation Solution
The design incorporates vertically stacked SRAM circuits with identical layouts, where bit lines and interconnections are routed horizontally in a single routing layer, and pull-up and pull-down voltage rails, along with word lines, are routed vertically through the stack, allowing for area-efficient and cost-effective memory design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional 3D IC fabrication with TSVs is used, then stacking of several circuits is enabled, but the large footprint of TSVs limits interconnection density and results in significant area overhead
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical routing by stacking multiple device tiers. Word lines are routed vertically through the stack using through-silicon vias, while bit lines remain in the horizontal plane. This dimensional change enables high-density interconnections without the area overhead of conventional TSVs, as the vertical routing shares the same footprint as the active devices.
2Manufacturing precision
If sequential 3D integration is used, then smaller vertical interconnect pitches are achieved, but the number of stacked vertical tiers is limited by manufacturing cost and complexity
Solution Approach 1:
The patent segments the interconnection function into two parts: vertical word line routing through TSVs and horizontal bit line routing in the active layer. This segmentation allows different routing strategies for different signal types, enabling simpler manufacturing compared to fully sequential 3D integration while achieving smaller effective pitch through the combination of vertical and horizontal routing.
Solution Approach 2:
The patent makes the bit line layer serve multiple functions: it provides horizontal interconnection within each tier and also serves as the interface for vertical word line connections through TSVs. This multi-functionality reduces the need for additional dedicated routing layers, simplifying the manufacturing process compared to sequential 3D integration.
3Area of stationary object
If 3D Nanofabric design is used, then area and cost reduction are achieved, but the layout must avoid all metal crossings except gate lines over channel area
Solution Approach 1:
The patent resolves the no-crossing constraint by moving the crossing function to the vertical dimension. Word lines cross bit lines through TSVs in the vertical direction, while bit lines remain horizontal in the active layer. This eliminates the need for complex planar routing avoidance while maintaining the area efficiency of 3D Nanofabric.
4Ease of manufacture
If 3D Nanofabric design is used, then all tiers must have identical layouts and perform the same logic operations, but this limits design flexibility
Solution Approach 1:
The patent segments the SRAM bit cell into functionally independent components: the 6T core circuit and the read path. This segmentation allows different tiers to have identical core circuits for manufacturing efficiency while enabling variation in read path configuration for design flexibility. The word line routing through TSVs provides the interface for selecting which tiers are actively read.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
According to an aspect there is provided a 3D IC comprising: a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit. The 3D IC further comprises: pull-up and pull-down voltage rails routed vertically through the stack of bit cells and connected to each bit cell of the stack; and first and second word lines routed vertically through the stack of bit cells and connected to each bit cell of the stack of bit cells.