CLB Logic Cell Architecture for Better Packing and Timing
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Solution Overview
Problem
Complex Logic Block (CLB) based Programmable Logic Devices (PLDs) face limitations in flexibility and efficiency for performing logic, register, arithmetic functions, and logic packing due to the constraints of existing logic cells.
Innovation Solution
The proposed solution involves arranging CLBs in a two-dimensional array with interconnect lines, each CLB having a first and second slice with enhanced logic cells, including Look Up Tables, arithmetic logic circuits, and output registers, allowing for improved logic efficiency by enabling different input sets for each cell and register feedback to balance delays and enhance packing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional logic cells with identical input sets are used in each slice, then the cell structure is simple and uniform, but logic packing efficiency is reduced and flexibility is limited
Solution Approach 1:
The patent implements different input sets for different logic cells within the same slice. Specifically, first logic cells receive inputs from a first set of input lines, while second logic cells receive inputs from a second set of input lines. This local differentiation allows each cell to be optimized for specific logic functions, improving packing efficiency without requiring complete structural redesign of all cells.
Solution Approach 2:
The slice is segmented into different types of logic cells with different input configurations. Each segment (logic cell type) is designed to handle specific logic functions efficiently. This segmentation allows the slice to perform multiple logic functions simultaneously with higher efficiency, resolving the contradiction between uniformity and specialization.
2Speed
If register feedback connections are added to balance delays, then timing performance is improved, but the cell structure becomes more complex
Solution Approach 1:
The patent introduces feedback connections from output registers back to the logic cell inputs. This feedback mechanism allows the circuit to balance propagation delays by recirculating signals through registered paths, improving timing performance. The feedback is selectively enabled through programming, so the complexity is managed through configuration rather than hardwired complexity.
3Adaptability or versatility
If multiple output registers are used to partition outputs, then logic functionality is enhanced and packing efficiency is improved, but the cell structure becomes more complex
Solution Approach 1:
The logic cells are designed with multi-functional output registers that can be programmed to perform different functions. The same physical register structure serves multiple purposes: partitioning outputs, balancing delays, and enabling different logic functions. This universality reduces the need for separate dedicated structures for each function, managing complexity while enhancing functionality.
4Productivity
If different input sets are provided to different logic cells, then logic packing efficiency is improved, but the interconnect structure becomes more complex
Solution Approach 1:
The patent introduces a new dimension to the interconnect structure by providing multiple sets of input lines (first set and second set) that can be selectively connected to different logic cells. This dimensional expansion of the input space allows efficient packing of different logic functions without requiring complex routing within a single input dimension. The interconnect complexity is managed by organizing inputs into distinct sets rather than creating complex point-to-point connections.
Data Source
AI summary
A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one of the logic cells includes one or more Look Up Tables for implanting logic functions on a set of inputs provided to the one logic cell and an arithmetic logic circuit configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain. In one embodiment, the logic cell further includes a first output register and a second output register and the set of outputs generated by the logic cell are partitioned among the first output register and the second output register. In another embodiment, an output of one of the registers is provided as an input to one of the Look Up Tables of the cell through a register feedback connection. In yet another embodiment, the set of inputs provided to a first and a second of the Look Up Tables are different, enabling a higher degree of logic efficiency or “packing” by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs. Finally, in another embodiment, the arithmetic logic circuit is capable of generating two SUM output signals.