Self-Timed Pulse Latches for Time Borrowing and Race-Through Control
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Solution Overview
Problem
Conventional flip-flop-based logic circuits face performance limitations due to the need to slow down clock frequency to accommodate the slowest combinational logic paths, leading to suboptimal timing performance and potential race conditions, with existing time borrowing schemes offering limited flexibility and complexity.
Innovation Solution
The introduction of configurable pulse latches that can operate as time borrowing flip-flops, utilizing a self-timed pulse generation circuit to generate adjustable clock pulses, and a configurable clock tree structure to distribute clock signals, allowing for dynamic adjustment of delay elements to optimize circuit performance and prevent race through conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional flip-flop-based logic circuits are used, then circuit timing behavior is straightforward to model and design is simplified, but clock frequency must be slowed down to accommodate the slowest combinational logic paths
Solution Approach 1:
The clock network is segmented into multiple independent clock trees, each serving specific logic paths. This allows different clock frequencies to be applied to different segments of the circuit, enabling fast paths to operate at higher frequencies while slow paths receive appropriate timing accommodation without limiting the entire circuit.
Solution Approach 2:
The invention introduces dynamic pulse generation where the width of clock pulses is adjusted based on the specific timing requirements of different logic paths. Configurable delay elements dynamically modify pulse widths to provide time borrowing for slow paths while maintaining high-speed operation in fast paths, resolving the contradiction between design simplicity and maximum operating speed.
2Speed
If time borrowing schemes are implemented to improve clock speed, then performance is enhanced, but it becomes difficult to obtain optimal performance due to limited clock delays available
Solution Approach 1:
The invention implements dynamically adjustable pulse generation circuits with configurable delay elements that can be programmed to provide different time borrowing amounts. This dynamic adaptability allows the circuit to optimize performance for different timing scenarios rather than being constrained by fixed delay values, directly addressing the limitation of conventional time borrowing schemes.
Solution Approach 2:
The invention changes the parameter of clock pulse width from a fixed value to a configurable parameter that can be adjusted based on the specific timing requirements of different logic paths. This parameter change enables flexible time borrowing optimization without being constrained by the limited delay options of conventional clock networks.
3Reliability
If fixed time borrowing flip-flops are used, then some time borrowing is provided, but optimal performance cannot be achieved in many circuits due to fixed and relatively small amount of time borrowing
Solution Approach 1:
The invention replaces fixed time borrowing flip-flops with dynamic pulse generation circuits that can adjust the amount of time borrowing based on actual circuit timing requirements. This dynamic capability allows the system to achieve optimal performance across various circuit configurations rather than being constrained by a fixed, limited time borrowing amount.
Solution Approach 2:
The configurable pulse generation circuit serves multiple functions: it can provide different amounts of time borrowing for different logic paths, adapt to various circuit timing requirements, and maintain reliable operation across different operating conditions. This multi-functionality replaces the need for multiple fixed time borrowing solutions with a single adaptable mechanism.
4Loss of time
If clock pulses are widened to support time borrowing operations, then time borrowing is enabled, but race through conditions may occur
Solution Approach 1:
The invention applies different clock pulse widths to different logic paths based on their specific timing requirements. Fast logic paths receive narrower pulses that prevent race through conditions, while slow logic paths receive wider pulses that enable adequate time borrowing. This localized differentiation resolves the contradiction between enabling time borrowing and preventing race conditions.
Solution Approach 2:
The configurable pulse generation circuit dynamically adjusts pulse widths based on the specific timing characteristics of each logic path. This dynamic adjustment ensures that pulses are wide enough to enable time borrowing where needed but not so wide as to cause race through conditions, maintaining reliability while enabling performance optimization.
Data Source
AI summary
Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.