Standard Cell Layout With Gate End-Cap Rules for Mixed-Width Cells

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Solution Overview

Problem

The use of standard cells with different heights in integrated circuit layouts leads to irregular patterns, waste of space, and reduced design flexibility, as well as increased power loss due to extended metal interconnections, limiting the efficiency of the automated layout process.

Innovation Solution

The design of an integrated circuit layout with standard cells of the same height but different widths, where the end-cap lengths of gate lines and dummy gate lines are optimized to prevent overlap during the gate line cut process, allowing for better control of channel current and manufacturability, and enabling the use of standard cells in the same routing block without adverse effects on current control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If standard cells with different heights are used to achieve different power levels, then design flexibility is improved, but irregular patterns and wasted space are produced in the layout

Engineering Contradiction:
Improvedesign flexibilityVSAvoidlayout space efficiency
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent changes the height parameter of standard cells to be uniform across different power levels, while compensating for power differentiation through other means (such as transistor width or gate line design). This parameter change eliminates the irregular patterns and space waste caused by varying cell heights, directly resolving the contradiction between design flexibility and layout space efficiency.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If standard cells with different heights are used for different powers, then power level differentiation is achieved, but the efficiency of automated layout process is reduced

Engineering Contradiction:
Improvepower level differentiationVSAvoidautomated layout process efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent standardizes the height parameter of all standard cells, creating a uniform grid structure that is highly compatible with automated layout tools. This uniformity allows automated placement and routing algorithms to operate more efficiently without needing to handle variable cell heights, thus improving productivity while maintaining power differentiation through alternative design parameters.

Inventive Principle:
Principle #35Parameter changes

3Shape

If standard cells are placed in different routing blocks to avoid irregular patterns, then layout regularity is improved, but design flexibility is limited

Engineering Contradiction:
Improvelayout regularityVSAvoiddesign flexibility
Core Design Contradiction:
ShapeVSAdaptability or versatility

Solution Approach 1:

The patent merges standard cells of different power levels into the same routing block by giving them uniform heights. This allows cells to be freely placed and connected within a single continuous routing block, enhancing design flexibility while maintaining layout regularity through the consistent cell height parameter.

Inventive Principle:
Principle #5Merging (Combining)

4Ease of operation

If metal interconnections are extended to connect standard cells in different routing blocks, then connectivity is achieved, but power loss increases

Engineering Contradiction:
ImproveconnectivityVSAvoidpower loss
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The patent extracts the need for extended metal interconnections by placing all standard cells within the same routing block. This eliminates the requirement for long-distance connections between separate routing blocks, thereby reducing power loss while maintaining full connectivity among cells through shorter, more efficient metal traces.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11984442B2Layout of integrated circuit
Publication Date: 2024.05.14 UNITED MICROELECTRONICS CORP
  • US11984442B2 patent drawing
  • US11984442B2 patent drawing
  • US11984442B2 patent drawing

AI summary

A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.