Array Substrate Signal Line Segmentation to Prevent Gate Line Arcing

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Solution Overview

Problem

During the manufacturing of array substrates, the accumulation of charges on gate lines can lead to arcing and breakage due to the arching phenomenon at bends when connecting with test lines, causing defects such as breakage.

Innovation Solution

The design of signal lines with a first trace in the display region and a second trace in the non-display region, where the second trace is divided into sub-traces disconnected from each other, with adjacent sub-traces electrically connected through transfer electrodes, prevents charge conduction to other traces, thereby avoiding arcing and potential breakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If signal lines are configured to extend from display region to non-display region, then electrical signals can be provided to pixel units, but charge accumulation occurs on gate lines causing arching phenomenon at bends

Engineering Contradiction:
Improvesignal line integrityVSAvoidcharge accumulation and arching
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The second trace in the non-display region is divided into at least two disconnected sub-traces. This segmentation prevents continuous charge conduction along the signal line, thereby eliminating the arching phenomenon that occurs at bends while still allowing electrical connection through transfer electrodes to the test line.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If gate lines are used to provide scanning signals to pixel units, then display functionality is achieved, but charge accumulation on gate lines causes arcing and breakage

Engineering Contradiction:
Improvescanning signal transmissionVSAvoidgate line durability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The gate line is segmented into a first trace in the display region and disconnected sub-traces in the non-display region. The segmentation prevents charge accumulation and arching while the first trace maintains scanning signal transmission to pixel units through the display region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Transfer electrodes serve as intermediaries to connect the disconnected sub-traces of the gate line to the test line. This allows the gate line to be segmented for safety while still maintaining electrical continuity for testing purposes through the intermediary transfer electrodes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If signal lines are disconnected into sub-traces, then charge conduction is prevented avoiding arcing, but manufacturing complexity increases

Engineering Contradiction:
Improvearc preventionVSAvoidsignal line structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Transfer electrodes are introduced as intermediary components to connect the disconnected sub-traces to the test line. While this adds components, the transfer electrodes are simple conductive structures that can be integrated into existing manufacturing processes, balancing arc prevention with manufacturing feasibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11955491B2Array substrate and manufacturing method thereof, motherboard and display device
Publication Date: 2024.04.09 BEIJING BOE DISPLAY TECH CO LTD
  • US11955491B2 patent drawing
  • US11955491B2 patent drawing
  • US11955491B2 patent drawing

AI summary

An array substrate and a manufacturing method thereof, a motherboard and a display device are disclosed. The array substrate has a display region and a non-display region, and includes a base substrate, and a plurality of signal lines and at least one transfer electrode that are on the base substrate. The plurality of signal lines extend from the display region to the non-display region along a first direction, at least one of the plurality of signal lines includes a first trace in the display region and a second trace in the non-display region, the second trace includes at least two sub-traces disconnected from each other, a sub-trace, close to the display region, of the at least two sub-traces of the second trace is directly connected with the first trace, and every two adjacent sub-traces of the second trace are electrically connected with each other.