Segmented Gate MOSFET Cells for Linear-Mode Thermal Runaway

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Modern power MOSFETs, especially trench and vertical double diffused MOSFETs, are susceptible to thermal runaway when operated in the linear regime due to a critical current density effect, where temperature increases lead to higher current density, causing further temperature rises and potential device failure.

Innovation Solution

The design separates cells into two types, where only the second cells operate in the linear mode, allowing for higher current density above or closer to the critical current density, reducing thermal runaway by distributing heat evenly across the device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If modern power MOSFETs are operated in the linear regime with small cell pitches to increase power handling capability, then the power handling capability is improved, but thermal runaway susceptibility increases due to operation below critical current density

Engineering Contradiction:
Improvepower handling capabilityVSAvoidthermal runaway susceptibility
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent divides the MOSFET cell structure into two distinct types: first cells with a first gate structure and second cells with a second gate structure. This segmentation allows independent control of different cell regions, enabling the second cells to operate in the linear regime at higher current densities above the critical threshold while the first cells handle saturated switching operations, thereby resolving the thermal runaway issue while maintaining power handling capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different gate structures and control strategies to different regions of the MOSFET device. The second cells are specifically designed and controlled to operate above critical current density in linear mode, creating a localized region with different operational characteristics from the first cells. This local quality differentiation enables thermal runaway prevention in specific areas without compromising overall device performance

Inventive Principle:
Principle #3Local quality

2Power

If the cell pitch is reduced to increase the number of cells and power handling, then the power handling capability is improved, but the current density control becomes more difficult leading to thermal runaway

Engineering Contradiction:
Improvepower handling capabilityVSAvoidcurrent density control
Core Design Contradiction:
PowerVSEase of operation

Solution Approach 1:

By segmenting the cell population into two types with different gate structures, the patent simplifies current density control despite reduced cell pitch. The separate gate lines enable independent control of second cells to maintain current density above the critical threshold, making operation easier rather than more difficult

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control capabilities through separate gate lines that can independently adjust the operating state of first and second cells. This dynamic control allows real-time optimization of current distribution and density, making the device easier to operate across varying conditions while maintaining thermal safety

Inventive Principle:
Principle #15Dynamics

3Power

If all cells are connected in parallel to increase current handling, then the current handling capability is improved, but thermal runaway risk increases due to uniform current distribution below critical density

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidthermal runaway risk
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent segments the parallel-connected cells into two distinct groups with different gate structures and control mechanisms. This segmentation allows the second cells to be specifically controlled to operate above critical current density, preventing thermal runaway while the first cells contribute to overall current handling capability through saturated switching

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By creating local quality differences between first and second cells through distinct gate structures, the patent enables non-uniform current distribution that prioritizes thermal safety. The second cells are locally optimized to operate in a thermally safe manner above critical density, while maintaining overall high current handling capability through the combined parallel structure

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates thermal runaway by ensuring the FET operates above or near the critical current density, reducing the likelihood of device failure and heat concentration.

Implementation Method 1

insulated gate field effect transistor

Methodology Applied
Scientific EffectField effect: Electric Field

Implementation Method 2

as temperature increases the resistance of the channel increases

Methodology Applied
Scientific EffectTemperature-dependent resistance: Electrical Resistance

Implementation Method 3

as temperature increases, the threshold voltage of the MOSFET decreases

Methodology Applied
Scientific EffectTemperature-dependent threshold voltage: Electrical Resistance

Implementation Method 4

increases current density, which causes an increase in temperature

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS20090212846A1Insulated gate field effect transistors
Publication Date: 2009.08.27 NEXPERIA BV
  • US20090212846A1 patent drawing
  • US20090212846A1 patent drawing
  • US20090212846A1 patent drawing

AI summary

A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.