Reconfigurable Core Layout With Register Buffers for Faster Mapping
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Solution Overview
Problem
Conventional reconfigurable logic semiconductor integrated circuits face challenges in efficiently mapping large-scale circuit functions due to increased combinations of functional units and logic elements, leading to mapping convergence issues and high resource requirements.
Innovation Solution
The semiconductor integrated circuit incorporates a plurality of reconfigurable cores with register circuits between them to temporarily hold and transfer output, allowing for efficient mapping of large-scale circuit functions by reducing wiring complexity and metastability, and enabling dynamic reconfiguration in a smaller area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all logic elements are respectively and directly interconnected to increase connection flexibility, then flexibility is improved, but wiring resource requirement increases enormously
Solution Approach 1:
The patent divides the reconfigurable logic semiconductor integrated circuit into multiple reconfigurable cores that are arranged separately. Each core is a self-contained unit with its own logic elements and interconnections, segmenting the overall system to reduce the wiring burden while maintaining flexibility through the modular core structure.
Solution Approach 2:
The patent introduces register circuits as intermediary elements between reconfigurable cores. These register circuits serve as buffers and coordination points, mediating the interactions between cores and reducing the need for direct complex wiring between all logic elements while maintaining system flexibility.
2Adaptability or versatility
If the scale of circuit functions is increased to meet multifunctional requirements, then functionality is improved, but mapping convergence becomes difficult due to increased combinations of functional units and logic elements
Solution Approach 1:
By dividing the large-scale circuit function into multiple reconfigurable cores, each handling a portion of the overall functionality, the patent reduces the combinatorial complexity within each core. This segmentation enables faster mapping convergence while maintaining the ability to implement large-scale multifunctional circuits.
3Adaptability or versatility
If multiple reconfigurable cores are installed on a single chip to construct large-scale reconfigurable logic semiconductor integrated circuit, then scalability is improved, but chip area increases
Solution Approach 1:
The patent merges multiple reconfigurable cores and register circuits onto a single semiconductor chip, creating an integrated large-scale reconfigurable logic system. This consolidation achieves scalability while optimizing chip area utilization through shared resources and compact arrangement of cores and interconnection structures.
Data Source
AI summary
A semiconductor integrated circuit (100) according to the present invention includes a plurality of reconfigurable cores (101) arranged separately from each other in a matrix, and a first group of register circuits (102) formed between a first and second reconfigurable cores included in the reconfigurable cores (101). Each of the reconfigurable cores (101) operates synchronously with clock signals and has a logic reconfiguration function, and includes a plurality of logic elements (201) that implements predetermined logic and programmable wiring (202 and 203) that interconnects the plurality of logic elements (201). The first group of register circuits (102) temporarily holds output from the first reconfigurable core and transfers the output to the second reconfigurable core.