Lookup Table Stage Layout for Balanced Input Delays
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Solution Overview
Problem
Existing lookup table (LUT) designs in integrated circuits suffer from unbalanced through-delays across input paths, leading to increased complexity and runtime in implementation software when trying to balance delays, hindering flexibility in pin assignments.
Innovation Solution
The implementation of a lookup table circuit with a differentiated first stage optimized for fast paths from LUT inputs to data outputs, and subsequent stages with introduced delays on control inputs to balance through-delays, using faster transistors and additional delay elements like decoders to reduce delays and improve multiplexer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a typical LUT design with multiple stages is used, then the LUT can implement any function of input signals, but the through-delays across different input paths are unbalanced
Solution Approach 1:
Delay elements are introduced in advance on specific input paths (particularly later stages) to pre-compensate for the inherent delay differences. This preliminary action ensures that all input paths arrive at balanced delays before reaching the output, resolving the unbalanced through-delays while maintaining full LUT functionality
Solution Approach 2:
Different delay characteristics are applied to different stages of the LUT. The first stage is optimized for fast paths from LUT inputs to data outputs, while subsequent stages have additional delay elements introduced on their control inputs. This local differentiation balances the overall through-delays across all input paths
2Loss of time
If delay balancing is attempted through software complexity, then through-delays can be balanced, but implementation software complexity and runtime increase
Solution Approach 1:
The LUT circuit automatically balances its own through-delays through the built-in delay elements and differentiated stage design. This self-service approach eliminates the need for complex software algorithms to calculate and adjust delays, as the hardware structure inherently provides balanced delays for all input paths
Solution Approach 2:
The delay characteristics of different stages are modified by introducing delay elements on control inputs of subsequent stages. This parameter change in the hardware structure creates inherent delay balance, replacing the need for complex software-based delay adjustment algorithms
3Loss of time
If delay balancing is attempted through pin assignment restrictions, then through-delays can be balanced, but flexibility in pin assignments is hindered
Solution Approach 1:
The differentiated first stage and subsequent stages with delay elements create uniform delay characteristics across all input paths regardless of pin assignment. This local optimization at each stage ensures that all inputs experience balanced delays, making pin assignments flexible without compromising delay balance
Data Source
AI summary
Lookup table circuits (LUTS) having multiple stages differently optimized to balance delays through the lookup table. A first multiplexing stage is optimized for a fast path from the control input to the data outputs, while a second and subsequent stage multiplexers are optimized for a fast path from data inputs to data outputs. In some embodiments, additional delay is introduced into the control inputs of the later stages, e.g., the LUT input paths with the smallest through-delays, in order to further balance the through-delays for the lookup table.